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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU3CG-2SBVA484I

XCZU3CG-2SBVA484I 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/4/29 9:51:35 鏌ョ湅 闁辫畝锛�29

XCZU3CG-2SBVA484I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq UltraScale+ MPSoC 绯诲垪涓殑涓�娆鹃珮绔� FPGA 鑺墖銆傝┎绯诲垪鑺墖闆嗘垚浜� ARM Cortex-A53 铏曠悊鍣ㄥ拰鍙法绋嬮倧杓硣婧�锛屾敮鎸佸鏅傝檿鐞�銆佸祵鍏ュ紡瑕栬銆佸伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)绛夊京(f霉)闆滄噳(y墨ng)鐢ㄣ�俋CZU3CG 灞簬 Zynq UltraScale+ 鐨� CG锛圕ost Grade锛夌増鏈�锛屽叿鏈夎純楂樼殑鎬у児姣斿拰鍔熻�楀劒(y艒u)鍖�锛岄仼鍚堝皪鎴愭湰鏁忔劅鐨勯珮鎬ц兘鎳�(y墨ng)鐢ㄥ牬鏅�銆�
銆�銆�瑭茶姱鐗囬噰鐢� TSMC 鐨� 16nm FinFET 宸ヨ棟鍒堕��锛屾彁渚涢珮瀵嗗害閭忚集鍠厓銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄤ互鍙婅睈瀵岀殑澶栬ō(sh猫)鎺ュ彛锛岃兘澶犳豢瓒冲緸閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂藉埌鑷嫊椐曢绛夊绋牁(l菒ng)鍩熺殑瑷�(sh猫)瑷堥渶姹�銆�

鍙冩暩(sh霉)

鍨嬭櫉锛歑CZU3CG-2SBVA484I
銆�銆�灏佽锛欶FGA484
銆�銆�宸ヨ棟锛�16nm FinFET
銆�銆�I/O 鏁�(sh霉)閲忥細2600
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 154K
銆�銆�RAM 瀹归噺锛�2.8Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2520
銆�銆�ADC 閫氶亾鏁�(sh霉)锛氱劇
銆�銆�铏曠悊鍣ㄦ牳锛氶洐鏍� ARM Cortex-A53 + 鍠牳 ARM Cortex-R5
銆�銆�鏈�楂樹富闋伙細ARM Cortex-A53 鏈�楂� 1.5GHz
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氶珮閬� 28Gbps
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�渚涢浕闆诲锛氬闆绘簮鍩熻ō(sh猫)瑷堬紝鏍稿績闆诲鐐� 0.85V

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XCZU3CG-2SBVA484I 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樺害闆嗘垚锛氬収(n猫i)缃洐鏍� ARM Cortex-A53 鍜屽柈鏍� ARM Cortex-R5 铏曠悊鍣�锛岄仼鐢ㄤ簬娣峰悎纭欢/杌熶欢鏋舵(g貌u)鐨勬噳(y墨ng)鐢ㄩ枊鐧�(f膩)銆�
銆�銆�2. 鍙法绋嬮倧杓細鎻愪緵澶ц(gu墨)妯＄殑 FPGA 閭忚集璩囨簮锛屾敮鎸佺敤鎴惰嚜瀹氱京绠楁硶鍜岀‖浠跺姞閫熷姛鑳�銆�
銆�銆�3. 楂橀�熼�ｆ帴鑳藉姏锛氭敮鎸侀珮閬� 28Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛岄仼閰� PCIe Gen4銆乁SB 3.1銆丼ATA 绛夊绋珮閫熷崝(xi茅)璀般��
銆�銆�4. 鍔熻�楀劒(y艒u)鍖栵細閲濆皪浣庡姛鑰楀牬鏅�茶鍎�(y艒u)鍖�锛岀壒鍒ラ仼鍚堥渶瑕侀珮鎬ц兘浣嗗彈闄愪簬鏁ｇ啽姊濅欢鐨勮ō(sh猫)瑷堛��
銆�銆�5. 瀹夊叏鎬э細鏀寔纭欢鍔犲瘑寮曟搸鍜屽畨鍏ㄥ暉鍕曞姛鑳�锛屼繚璀风郴绲�(t菕ng)鍏嶅彈鎯℃剰鏀绘搳銆�
銆�銆�6. 鏄撶敤鎬э細閰嶅悎 Xilinx 鎻愪緵鐨� Vivado Design Suite 鍜� SDK 闁嬬櫦(f膩)宸ュ叿锛岃兘澶犲揩閫熷鐝�(xi脿n)寰�(f霉)闆滅殑 SoC 瑷�(sh猫)瑷�銆�

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XCZU3CG-2SBVA484I 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宓屽叆寮忚▓绠楋細濡傚伐妤�(y猫) PC銆佹鍣ㄤ汉鎺у埗鍠厓绛夈��
銆�銆�2. 瑕栬铏曠悊锛氱敤浜庢鍣ㄨ瑕�銆佸湒鍍忚瓨鍒ュ強瑕栭牷鐩�(ji膩n)鎺с��
銆�銆�3. 閫氫俊瑷�(sh猫)鍌欙細閬╃敤浜庣劇绶氬熀绔�銆佺恫(w菐ng)绲�(lu貌)浜ゆ彌姗熷拰璺敱鍣�銆�
銆�銆�4. 姹借粖闆诲瓙锛氳紨鍔╅椐涚郴绲�(t菕ng)銆佽粖杓変俊鎭妯傜郴绲�(t菕ng)銆�
銆�銆�5. 閱�(y墨)鐧傝ō(sh猫)鍌欙細濡傝秴鑱叉尝鎴愬儚鍎�銆佺梾浜虹洠(ji膩n)璀峰剙绛�銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栵細PLC 鎺у埗鍣�銆侀亱鍕曟帶鍒剁郴绲�(t菕ng)銆�
銆�銆�7. 鐗╄伅(li谩n)缍�(w菐ng) (IoT)锛氭櫤鑳界恫(w菐ng)闂�(gu膩n)銆侀倞绶ｈ▓绠楃瘈(ji茅)榛�銆�

鏇夸唬鍨嬭櫉

XCZU3EG-2SFVC760I, XCZU4EV-2FGGA676I, XCZU5EV-2FFVG1156I

xczu3cg-2sbva484i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xczu3cg-2sbva484i鍙冩暩(sh霉)

  • 鐝�(xi脿n)鏈夋暩(sh霉)閲�0鐝�(xi脿n)璨ㄦ煡鐪嬩氦鏈�
  • 鍍规牸1 : 锟�5,684.18000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC CG
  • 鍖呰鎵樼洡
  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
  • 鏋舵(g貌u)MCU锛孎(xi脿n)PGA
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  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
  • 閫熷害533MHz锛�1.3GHz
  • 涓昏灞��Zynq?UltraScale+? FPGA锛�154K+ 閭忚集鍠厓
  • 宸ヤ綔婧害-40掳C ~ 100掳C锛圱J锛�
  • 灏佽/澶栨484-BFBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�484-FCBGA锛�19x19锛�