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XCZU6CG-2FFVC900E 鏄竴娆惧熀浜� Xilinx Zynq UltraScale+ MPSoC 绯诲垪鐨勯珮绔� FPGA 鑺墖銆傝┎鑺墖绲愬悎浜� ARM 铏曠悊绯荤当(t菕ng)鑸囧彲绶ㄧ▼閭忚集锛屾敮鎸佸绋珮鎬ц兘鎳夌敤锛屼緥濡傚祵鍏ュ紡瑕栬銆佸伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)浠ュ強閫氫俊鍩虹瑷柦绛夈��
銆�銆�瑭插櫒浠堕噰鐢� 16nm FinFET 宸ヨ棟鍒堕��锛屽叿鍌欏挤澶х殑铏曠悊鑳藉姏銆佷綆鍔熻�楀拰楂樺害闆嗘垚鐨勭壒榛�锛屽悓鏅傛彁渚涜睈瀵岀殑鎺ュ彛鍜屽瑷伕闋咃紝鑳藉婊胯冻澶氭ǎ鍖栫殑瑷▓闇�姹�銆�
鍨嬭櫉锛歑CZU6CG-2FFVC900E
銆�銆�绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�宸ヨ棟锛�16nm FinFET
銆�銆�鍏�(n猫i)鏍革細闆欐牳 ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�FPGA 鏋舵锛歎ltraScale+
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銆�銆�RAM锛氶珮閬� 3.3MB 鐨勭墖涓婂瓨鍎插櫒
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銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 2048 鍊嬬敤鎴� I/O
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 0.85V锛孖/O 闆诲 1.8V/3.3V
銆�銆�灏佽锛欶FVC900E
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCZU6CG-2FFVC900E 绲愬悎浜� ARM 铏曠悊绯荤当(t菕ng)鑸� FPGA 鍙法绋嬮倧杓紝浣垮叾鎴愮偤楂樻�ц兘宓屽叆寮忕郴绲�(t菕ng)鐨勭悊鎯抽伕鎿�銆�
銆�銆�1. 楂樻�ц兘铏曠悊锛氶洐鏍� ARM Cortex-A53 鎻愪緵寮峰ぇ鐨勯�氱敤瑷堢畻鑳藉姏锛岃�岄洐鏍� ARM Cortex-R5 鍓囧皥娉ㄤ簬瀵︽檪鎺у埗浠诲嫏銆�
銆�銆�2. FPGA 鍙法绋嬮倧杓細鍩轰簬 UltraScale+ 鏋舵鐨� FPGA 閭忚集濉婂厑瑷辩敤鎴惰嚜瀹氱京纭欢鍔犻�熷姛鑳姐��
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銆�銆�5. 浣庡姛鑰楄ō瑷堬細閫氶亷鍕曟厠(t脿i)闆绘簮绠＄悊鎶�琛撻’钁楅檷浣庢暣楂斿姛鑰�銆�
銆�銆�6. 璞愬瘜鐨勫瑷敮鎸侊細鍖呮嫭 USB銆佷互澶恫(w菐ng)銆丼ATA 绛夊绋父鐢ㄦ帴鍙�锛岀啊鍖栫郴绲�(t菕ng)闁嬬櫦(f膩)閬庣▼銆�
XCZU6CG-2FFVC900E 寤ｆ硾鎳夌敤浜庡鍊嬮牁鍩燂細
銆�銆�1. 宓屽叆寮忚瑕猴細鐢ㄤ簬宸ユキ(y猫)鐩告銆侀啱(y墨)鐧傛垚鍍忚ō鍌欏強鏅鸿兘鐩�(ji膩n)鎺х郴绲�(t菕ng)銆�
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銆�銆�4. 姹借粖闆诲瓙锛氶仼鐢ㄤ簬楂樼礆椐曢杓斿姪绯荤当(t菕ng)锛圓DAS锛夊拰鑷嫊椐曢骞宠嚭銆�
銆�銆�5. 鏁�(sh霉)鎿�(j霉)涓績锛氫綔鐐哄姞閫熷崱鐨勬牳蹇冪祫浠�锛岀敤浜� AI 鎺ㄧ悊銆佹暩(sh霉)鎿�(j霉)鍒嗘瀽绛夊牬鏅�銆�
銆�銆�6. 鐗╄伅(li谩n)缍�(w菐ng)锛圛oT锛夛細鍦ㄩ倞绶ｈ▓绠楃瘈(ji茅)榛炰腑鎻愪緵鏈湴鍖栬檿鐞嗚兘鍔�銆�
XCZU7EV-2FFVC1156E
銆�銆�XCZU5EV-2FFVG900E
銆�銆�XCZU4CG-2FFVC896E
