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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU6EG-2FFVC900E

XCZU6EG-2FFVC900E 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/4/29 9:46:45 鏌ョ湅 闁辫畝锛�30

XCZU6EG-2FFVC900E鏄疿ilinx鍏徃鎺ㄥ嚭鐨刄ltraScale+绯诲垪涓殑楂樻�ц兘FPGA鑺墖銆傝┎鑺墖鍩轰簬16nm宸ヨ棟鍒剁▼锛岄噰鐢╖ynq UltraScale+ MPSoC鏋舵(g貌u)锛岄泦鎴愪簡鍙法绋嬮倧杓�銆佽檿鐞嗗櫒绯荤当(t菕ng)浠ュ強澶氱ó灏堢敤纭欢妯″銆俋CZU6EG鍨嬭櫉灞簬eMPSoC锛堝祵鍏ュ紡澶氳檿鐞嗙郴绲�(t菕ng)绱氳姱鐗囷級绯诲垪锛岀壒鍒ラ仼鍚堥渶瑕侀珮瑷堢畻鎬ц兘鍜屼綆鍔熻�楃殑鎳�(y墨ng)鐢ㄥ牬鏅�銆�
銆�銆�瑭茶姱鐗囬仼鐢ㄤ簬閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆侀珮绱氶椐涘摗杓斿姪绯荤当(t菕ng)锛圓DAS锛�銆佸伐妤�(y猫)鑷嫊鍖�銆佽闋荤洠(ji膩n)鎺т互鍙婂叾浠栧皪瀵︽檪铏曠悊鑳藉姏瑕佹眰杓冮珮鐨勯牁(l菒ng)鍩熴��

鍙冩暩(sh霉)

鍨嬭櫉锛歑CZU6EG-2FFVC900E
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�鍏�(n猫i)鏍告灦妲�(g貌u)锛欰RM Cortex-A53锛堝洓鏍革級 + ARM Cortex-R5锛堥洐鏍革級
銆�銆�鍙法绋嬮倧杓硣婧愶細绱�237K閭忚集鍠厓
銆�銆�DSP Slice鏁�(sh霉)閲忥細2880鍊�
銆�銆�濉奟AM瀹归噺锛氱磩11.4MB
銆�銆�鐗囦笂瀛樺劜鍣細2GB DDR4锛堥泦鎴愬湪灏佽鍏�(n猫i)锛�
銆�銆�PCIe鎺ュ彛锛氭敮鎸丟en3 x8
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂�32.75Gbps
銆�銆�I/O寮曡叧鏁�(sh霉)锛�1066鍊嬬敤鎴禝/O
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽椤炲瀷锛欶FVC900

鐗规��

XCZU6EG-2FFVC900E鐨勬牳蹇冪壒鎬у湪浜庡叾楂樺害闆嗘垚鐨勬灦妲�(g貌u)瑷�(sh猫)瑷�銆傚畠绲�(ji茅)鍚堜簡鍙法绋嬮倧杓拰宓屽叆寮忚檿鐞嗗櫒绯荤当(t菕ng)锛屽厑瑷遍枊鐧�(f膩)鑰呴潏娲诲湴閰嶇疆纭欢鍔犻�熸ā濉婂拰杌熶欢鍔熻兘銆�
銆�銆�1. 铏曠悊鍣ㄥ瓙绯荤当(t菕ng)鍖呮嫭鍥涙牳ARM Cortex-A53鍜岄洐鏍窤RM Cortex-R5锛岃兘澶犳豢瓒冲鏅傛帶鍒惰垏楂樻�ц兘瑷堢畻闇�姹傘��
銆�銆�2. FPGA閭忚集閮ㄥ垎鎻愪緵浜嗚睈瀵岀殑鍙法绋嬭硣婧�锛屽閭忚集鍠厓銆丏SP Slice鍜孊lock RAM锛岄仼鐢ㄤ簬寰�(f霉)闆滅畻娉曠殑纭欢瀵︾従(xi脿n)銆�
銆�銆�3. 鍏�(n猫i)缃殑HBM锛堥珮甯跺鍏�(n猫i)瀛橈級鏀寔楂橀仈(d谩)2GB鐨凞DR4瀛樺劜瀹归噺锛岄’钁楁彁鍗囦簡鏁�(sh霉)鎿�(j霉)鍚炲悙閲�銆�
銆�銆�4. 楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼鍙仈(d谩)32.75Gbps锛岀偤楂橀�熺恫(w菐ng)绲�(lu貌)鍜屾暩(sh霉)鎿�(j霉)鍌宠几鎻愪緵寮�(qi谩ng)澶ф敮鎸�銆�
銆�銆�5. 鎻愪緵澶氱ó澶栬ō(sh猫)鎺ュ彛鏀寔锛屽寘鎷琍CIe Gen3 x8銆佸崈鍏嗕互澶恫(w菐ng)绛�锛屾豢瓒冲妯ｅ寲鎳�(y墨ng)鐢ㄩ渶姹傘��

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XCZU6EG-2FFVC900E寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細鍙敤浜庡熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙(j墨)绛夎ō(sh猫)鍌欎腑锛屽鐝�(xi脿n)淇¤櫉铏曠悊鍜屽崝(xi茅)璀拌綁(zhu菐n)鎻�銆�
銆�銆�2. 鑷嫊椐曢鑸嘇DAS锛氭啈鍊熷挤(qi谩ng)澶х殑瀵︽檪铏曠悊鑳藉姏鍜岃睈瀵岀殑鎺ュ彛璩囨簮锛岄仼鐢ㄤ簬鍌虫劅鍣ㄨ瀺鍚�銆佸湒鍍忚瓨鍒ョ瓑浠诲嫏(w霉)銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬姗�(j墨)鍣ㄤ汉鎺у埗銆侀亱(y霉n)鍕曟帶鍒跺拰宸ユキ(y猫)鐗╄伅(li谩n)缍�(w菐ng)缍�(w菐ng)闂�(gu膩n)銆�
銆�銆�4. 閱�(y墨)鐧傛垚鍍忥細鏀寔楂樺垎杈ㄧ巼鍦栧儚铏曠悊鍜屽鏅傛暩(sh霉)鎿�(j霉)鍒嗘瀽銆�
銆�銆�5. 瑕栭牷鐩�(ji膩n)鎺э細瀵︾従(xi脿n)楂樻竻瑕栭牷绶ㄨВ纰笺�佹櫤鑳藉垎鏋愮瓑鍔熻兘銆�

鏇夸唬鍨嬭櫉

XCZU7EV-2FFVC1156E
銆�銆�XCZU5EV-2FFVG900E
銆�銆�XCZU4EG-2FFVC896E

xczu6eg-2ffvc900e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xczu6eg-2ffvc900e鍙冩暩(sh霉)

  • 鐝�(xi脿n)鏈夋暩(sh霉)閲�0鐝�(xi脿n)璨ㄦ煡鐪嬩氦鏈�
  • 鍍规牸1 : 锟�28,112.84000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
  • 鍖呰鎵樼洡
  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
  • 鏋舵(g貌u)MCU锛孎(xi脿n)PGA
  • 鏍稿績铏曠悊鍣�甯� CoreSight? 鐨勫洓鏍� ARM? Cortex?-A53 MPCore?锛屽付 CoreSight? 鐨勯洐鏍� ARM?Cortex?-R5锛孉RM Mali?-400 MP2
  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
  • 閫熷害533MHz锛�600MHz锛�1.3GHz
  • 涓昏灞��Zynq?UltraScale+? FPGA锛�469K+ 閭忚集鍠厓
  • 宸ヤ綔婧害0掳C ~ 100掳C锛圱J锛�
  • 灏佽/澶栨900-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�900-FCBGA锛�31x31锛�