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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU7EV-2FFVC1156E

XCZU7EV-2FFVC1156E 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/5/13 11:56:20 鏌ョ湅 闁辫畝锛�26

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宸ヨ棟锛�16nm
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銆�銆�FPGA鏋舵(g貌u)锛歎ltraScale+
銆�銆�閭忚集鍠厓锛氱磩210K
銆�銆�DSP Slice锛�2800鍊�
銆�銆�Block RAM锛氱磩25MB
銆�銆�楂橀�熸敹鐧�(f膩)鍣細32Gbps
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽锛欶FVC1156

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鏇夸唬鍨嬭櫉

XCZU7EG-2FFVC1156E
銆�銆�XCZU9EG-2FFVC1156E

xczu7ev-2ffvc1156e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xczu7ev-2ffvc1156e鍙冩暩(sh霉)

  • 鐝�(xi脿n)鏈夋暩(sh霉)閲�0鐝�(xi脿n)璨ㄦ煡鐪嬩氦鏈�
  • 鍍规牸1 : 锟�35,593.30000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EV
  • 鍖呰鎵樼洡
  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
  • 鏋舵(g貌u)MCU锛孎(xi脿n)PGA
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  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
  • 閫熷害533MHz锛�600MHz锛�1.3GHz
  • 涓昏灞��Zynq?UltraScale+? FPGA锛�504K+ 閭忚集鍠厓
  • 宸ヤ綔婧害0掳C ~ 100掳C锛圱J锛�
  • 灏佽/澶栨1156-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�1156-FCBGA锛�35x35锛�