鏅傞枔锛�2025/4/28 16:52:09
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XCZU9EG-1FFVB1156E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq UltraScale+ MPSoC 绯诲垪涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪鑺墖闆嗘垚浜� ARM 铏曠悊鍣ㄨ垏鍙法绋嬮倧杓�锛岄仼鍚堢敤浜庨渶瑕侀珮鎬ц兘瑷堢畻鍜岄潏娲荤‖浠跺姞閫熺殑鎳夌敤鍫存櫙銆俋CZU9EG 閰嶅倷浜嗗洓鏍� ARM Cortex-A53 鍜岄洐鏍� ARM Cortex-R5 铏曠悊鍣�锛屽悓鏅傚叿鏈夎睈瀵岀殑 DSP 妯″鍜屽ぇ瀹归噺鐨� FPGA 閭忚集璩囨簮銆�
銆�銆�閫欐鑺墖鏀寔澶氱ó楂橀�熸帴鍙ｆ婧�锛屽寘鎷� PCIe銆乁SB銆佸崈鍏嗕互澶恫(w菐ng)绛�锛屽苟涓斿叿鍌欏挤澶х殑瑕栭牷鍜屽湒鍍忚檿鐞嗚兘鍔涳紝寤ｆ硾鎳夌敤浜庡祵鍏ュ紡瑕栬銆佸伐妤�(y猫)鑷嫊鍖�銆侀�氫俊鍩虹瑷柦绛夐牁鍩�銆�
鍨嬭櫉锛歑CZU9EG-1FFVB1156E
銆�銆�绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�铏曠悊鍣細鍥涙牳 ARM Cortex-A53锛堟渶楂� 1.0/1.2/1.5GHz锛夛紝闆欐牳 ARM Cortex-R5
銆�銆�FPGA 鏋舵(g貌u)锛歎ltraScale+
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 244K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2520
銆�銆�瀛樺劜鍣細鐗囦笂 RAM锛堢磩 7.8MB锛�
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�1156
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃�锛岄渶澶栨帴
銆�銆�灏佽椤炲瀷锛欶FVB1156
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�宸ヨ棟鍒剁▼锛�16nm
XCZU9EG-1FFVB1156E 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樺害闆嗘垚锛氬皣鎳夌敤铏曠悊鍣紙AP锛夈�佸鏅傝檿鐞嗗櫒锛圧P锛夊拰鍙法绋嬮倧杓紙PL锛夌祼(ji茅)鍚堝湪涓�鍊嬭姱鐗囦腑锛屽鐝�(xi脿n)杌熺‖浠跺崝(xi茅)鍚岃ō瑷堛��
銆�銆�2. 澶氭牳铏曠悊鑳藉姏锛欰RM Cortex-A53 鎻愪緵閫氱敤瑷堢畻鎬ц兘锛岃�� Cortex-R5 鍓囬嚌灏嶅鏅傛帶鍒朵换鍕欓�茶浜嗗劒(y艒u)鍖�銆�
銆�銆�3. 寮峰ぇ鐨� DSP 鏀寔锛�2520 鍊� DSP Slice 鑳藉楂樻晥鍩�(zh铆)琛屾诞榛為亱绠楀拰淇¤櫉铏曠悊浠诲嫏銆�
銆�銆�4. 楂橀�熸帴鍙ｆ敮鎸侊細鏀寔 PCIe Gen3銆乁SB 3.0銆丼ATA銆佸崈鍏嗕互澶恫(w菐ng)绛夊绋珮閫熸帴鍙�銆�
銆�銆�5. 瀹夊叏鍔熻兘锛氬収(n猫i)缃姞瀵嗗紩鎿庡拰瀹夊叏鍟熷嫊姗熷埗锛岀⒑淇濈郴绲�(t菕ng)瀹夊叏鎬�銆�
銆�銆�6. 瑕栭牷铏曠悊鍠厓锛氭敮鎸� H.264/H.265 绶ㄨВ纰�锛岄仼鐢ㄤ簬澶氬獟楂旀噳鐢ㄣ��
銆�銆�7. 鍙摯灞曟�э細閫氶亷 FPGA 閮ㄥ垎鍙互鏍规摎(j霉)闇�姹傚畾鍒剁‖浠跺姞閫熸ā濉娿��
銆�銆�8. 浣庡姛鑰楄ō瑷堬細閲囩敤 16nm FinFET 宸ヨ棟锛屽湪淇濊瓑鎬ц兘鐨勫悓鏅傞檷浣庡姛鑰�銆�
XCZU9EG-1FFVB1156E 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 宓屽叆寮忚瑕猴細濡傛鍣ㄨ瑕�銆佹櫤鑳芥敐鍍忛牠銆侀潰閮ㄨ瓨鍒ョ瓑銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細鍖呮嫭宸ユキ(y猫)鐗╄伅(li谩n)缍�(w菐ng)缍�(w菐ng)闂溿�佹鍣ㄤ汉鎺у埗銆侀爯娓�х董璀风郴绲�(t菕ng)绛�銆�
銆�銆�3. 閫氫俊鍩虹瑷柦锛氫緥濡傚皬鍨嬪熀绔�銆佺恫(w菐ng)绲¤矾鐢卞櫒銆佹暩(sh霉)鎿�(j霉)鍖呰檿鐞嗚ō鍌欑瓑銆�
銆�銆�4. 姹借粖闆诲瓙锛氶珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛�銆佽粖杓変俊鎭妯傜郴绲�(t菕ng)绛�銆�
銆�銆�5. 閱�(y墨)鐧傝ō鍌欙細瓒呰伈娉㈣ō鍌欍�侀仩绋嬭ê鏂风郴绲�(t菕ng)銆佷究鏀滃紡閱�(y墨)鐧傚剙鍣ㄧ瓑銆�
銆�銆�6. 鑸┖鑸ぉ鑸囧湅闃诧細闆烽仈绯荤当(t菕ng)銆佽(w猫i)鏄熼�氫俊銆佺劇浜虹郴绲�(t菕ng)绛�銆�
銆�銆�7. 閭婄罚瑷堢畻锛氬垎甯冨紡瑷堢畻绡�(ji茅)榛炪�丄I 鎺ㄧ悊鍔犻�熷櫒绛�銆�
XCZU9EG-2FFVB1156E
銆�銆�XCZU9EV-1FFVB1156E
銆�銆�XCZU7EV-1FFVC1156E
