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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU9EG-2FFVB1156E

XCZU9EG-2FFVB1156E 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/5/24 13:58:25 鏌ョ湅 闁辫畝锛�18

XCZU9EG-2FFVB1156E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖锛屽熀浜� 16nm FinFET 宸ヨ棟鍒堕��銆傝┎鍣ㄤ欢灞簬 Zynq UltraScale+ MPSoC 绯诲垪锛岄泦鎴愪簡 ARM 铏曠悊鍣ㄧ郴绲�(t菕ng)鍜屽彲绶ㄧ▼閭忚集璩囨簮锛岄仼鐢ㄤ簬楂樻�ц兘宓屽叆寮忚▓绠�銆侀�氫俊銆佸伐妤�(y猫)鎺у埗鍜屽湒鍍忚檿鐞嗙瓑鎳�(y墨ng)鐢ㄩ牁(l菒ng)鍩�銆�
銆�銆�瑭茶姱鐗囧叿鏈夐珮闆嗘垚搴︺�佷綆鍔熻�椾互鍙婂挤澶х殑骞惰铏曠悊鑳藉姏锛屾敮鎸佸绋帴鍙ｅ崝(xi茅)璀板拰寰�(f霉)闆滅畻娉曞鐝�(xi脿n)銆�

鍙冩暩(sh霉)

鍨嬭櫉锛歑CZU9EG-2FFVB1156E
銆�銆�绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�宸ヨ棟绡�(ji茅)榛烇細16nm
銆�銆�FPGA 鏋舵(g貌u)锛歎ltraScale+
銆�銆�閭忚集鍠厓锛氱磩 344,400
銆�銆�DSP Slice锛�2,520
銆�銆�Block RAM锛氱磩 35.8MB
銆�銆�鍏�(n猫i)閮� Flash锛氱劇
銆�銆�PS锛堣檿鐞嗗櫒绯荤当(t菕ng)锛夛細闆欐牳 ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 1,664 鍊�
銆�銆�灏佽椤炲瀷锛欶FVB1156
銆�銆�閰嶇疆妯″紡锛氬缃潪鏄撳け鎬у瓨鍎插櫒

鐗规��

XCZU9EG-2FFVB1156E 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 闆嗘垚闆欐牳 ARM Cortex-A53 鎳�(y墨ng)鐢ㄨ檿鐞嗗櫒锛屼富闋婚珮閬� 1.5GHz锛岄仼鍚堥亱琛屾搷浣滅郴绲�(t菕ng)鍜岄珮绱氳粺浠跺姛鑳�銆�
銆�銆�2. 鍏�(n猫i)缃洐鏍� ARM Cortex-R5 瀵︽檪铏曠悊鍣�锛屽皥鐐哄鏅備换鍕�(w霉)鍎�(y艒u)鍖�銆�
銆�銆�3. 鎻愪緵璞愬瘜鐨勭‖浠跺姞閫熸ā濉�锛屽瑕栭牷绶ㄧ⒓/瑙ｇ⒓鍠厓銆佸姞瀵嗗紩鎿庡拰瀹夊叏鍟熷嫊鏀寔銆�
銆�銆�4. 鏀寔楂橀�熶覆琛屾帴鍙�锛屼緥濡� PCIe Gen3 x8銆乁SB 3.0 鍜� 100G Ethernet MAC銆�
銆�銆�5. 鍙法绋嬮倧杓崁(q奴)鍩熼噰鐢� UltraScale+ 鏋舵(g貌u)锛屽叿鍌欐洿楂樼殑鎬ц兘鍜屾洿浣庣殑寤堕伈銆�
銆�銆�6. 鏀寔 LPDDR4銆丏DR4 鍜� DDR3 鍏�(n猫i)瀛樻帴鍙ｏ紝婊胯冻涓嶅悓鎳�(y墨ng)鐢ㄥ牬鏅殑闇�姹�銆�
銆�銆�7. 寮峰ぇ鐨勯浕婧愮鐞嗗拰鐔辫ō(sh猫)瑷�锛岀⒑淇濆湪鍚勭ó鐠�(hu谩n)澧冧笅绌�(w臎n)瀹氶亱琛屻��

鎳�(y墨ng)鐢�

XCZU9EG-2FFVB1浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛屼緥濡傛鍣ㄨ瑕�銆佹櫤鑳芥敐鍍忛牠鍜岃嚜鍕曢椐涜紨鍔╃郴绲�(t菕ng)銆�
銆�銆�2. 鐒＄窔閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤紝鍖呮嫭 5G 鍩虹珯鍜屽皬鍨嬭渹绐╃恫(w菐ng)绲�(lu貌)銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栬ō(sh猫)鍌�锛屽 PLC 鎺у埗鍣�銆侀亱鍕曟帶鍒跺櫒鍜屾鍣ㄤ汉銆�
銆�銆�4. 閱�(y墨)鐧傛垚鍍忚ō(sh猫)鍌�锛岀敤浜庤秴鑱叉尝銆丆T 鎺冩弿鍎�鍜屽叾浠栭渶瑕侀珮鎬ц兘淇¤櫉铏曠悊鐨勬噳(y墨ng)鐢ㄣ��
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃�锛屾彁渚涢珮鍙潬鎬у拰瀵︽檪鏁�(sh霉)鎿�(j霉)铏曠悊鑳藉姏銆�
銆�銆�6. 姹借粖闆诲瓙锛屾敮鎸� ADAS锛堥珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛夊拰鑷嫊椐曢鍔熻兘銆�

鏇夸唬鍨嬭櫉

XCZU9EG-2FFVC1156E
銆�銆�XCZU9EG-2FFVB1156I
銆�銆�XCZU9EG-2FFVC1156I

xczu9eg-2ffvb1156e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xczu9eg-2ffvb1156e鍙冩暩(sh霉)

  • 鐝�(xi脿n)鏈夋暩(sh霉)閲�16鐝�(xi脿n)璨�
  • 鍍规牸1 : 锟�39,084.18000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
  • 鍖呰鎵樼洡
  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
  • 鏋舵(g貌u)MCU锛孎(xi脿n)PGA
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  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
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  • 宸ヤ綔婧害0掳C ~ 100掳C锛圱J锛�
  • 灏佽/澶栨1156-BBGA锛孎(xi脿n)CBGA
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