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闁辫畝锛�45
XCZU9EG-3FFVC900E鏄疿ilinx鍏徃鎺ㄥ嚭鐨刄ltraScale+绯诲垪涓殑楂樼MPSoC锛堝铏曠悊鍣ㄧ郴绲�(t菕ng)鑺墖锛�銆傝┎鑺墖鍩轰簬16nm FinFET宸ヨ棟鍒堕��锛岄泦鎴愪簡ARM Cortex-A53鎳夌敤铏曠悊鍣ㄥ拰Cortex-R5瀵︽檪铏曠悊鍣紝鍚屾檪閭勫寘鍚簡鍙法绋嬮倧杓硣婧�銆傞�欐鍣ㄤ欢閬╁悎鎳夌敤浜庨珮甯跺銆佷綆寤堕伈鐨勫牬鏅�锛屼緥濡�5G鐒＄窔閫氫俊銆侀珮绱氶椐涘摗杓斿姪绯荤当(t菕ng)(ADAS)銆佸伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)绛夐牁鍩�銆�
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鍨嬭櫉锛歑CZU9EG-3FFVC900E
銆�銆�宸ヨ棟锛�16nm
銆�銆�鍏�(n猫i)鏍革細闆欐牳 ARM Cortex-A53 (64-bit)锛岄洐鏍� ARM Cortex-R5
銆�銆�FPGA鏋舵锛歎ltraScale+
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱�238K鍊�
銆�銆�DSP Slice鏁�(sh霉)閲忥細4720鍊�
銆�銆�Block RAM瀹归噺锛氱磩22MB
銆�銆�瀛樺劜鎺ュ彛锛氭敮鎸丏DR4/LPDDR4
銆�銆�灏佽椤炲瀷锛欶FVC900
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�I/O闆诲锛�1.8V, 1.5V, 1.2V, 0.9V
銆�銆�鍔熻�楋細鍏稿瀷鍊肩磩鐐�10W锛堝彇姹轰簬浣跨敤鎯呮硜锛�
XCZU9EG-3FFVC900E鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘铏曠悊瀛愮郴绲�(t菕ng)锛氶泦鎴愪簡闆欐牳ARM Cortex-A53鍜岄洐鏍窤RM Cortex-R5锛岃兘澶犲悓鏅傛敮鎸侀�氱敤瑷堢畻鍜屽鏅傛帶鍒朵换鍕欍��
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銆�銆�4. 瀹夊叏鎬у姛鑳斤細鏀寔AES鍔犲瘑銆丼HA鍝堝笇绠楁硶绛夊绋畨鍏ㄥ崝(xi茅)璀�锛屼繚璀锋暩(sh霉)鎿�(j霉)鍜岀郴绲�(t菕ng)鐨勫畬鏁存��銆�
銆�銆�5. 寤ｆ硾鐨勫瑷帴鍙ｏ細鍖呭惈PCIe Gen3銆乁SB銆丼ATA銆佷互澶恫(w菐ng)绛夎睈瀵岀殑鎺ュ彛閬搁爡锛屼究浜庨�ｆ帴澶栭儴瑷倷銆�
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銆�銆�7. 鍙潬鎬у拰鑰愮敤鎬э細鍏峰倷鑷銆佺尘閷瓑鍔熻兘锛岃兘澶犲湪妤电鐠�(hu谩n)澧冧笅绌�(w臎n)瀹氶亱琛�銆�
XCZU9EG-3FFVC900E寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛�5G鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙绛�銆�
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銆�銆�4. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉㈣ō鍌�銆丆T鎺冩弿鍎�銆�
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銆�銆�7. 鍦嬮槻鑸囪埅澶╋細闆烽仈绯荤当(t菕ng)銆佽(w猫i)鏄熼�氫俊瑷倷銆�
XCZU7EV-2FFVC1156E
銆�銆�XCZU11EG-2FFVB1156E
銆�銆�XCZU19EG-2FFVC1760E
