EP1S10F672C6N 鏅傞枔锛�2023/8/1 11:11:30 闁辫畝锛�407

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鐢�(ch菐n)鍝佸瀷铏�	EP1S10F672C6N
鎻忚堪	IC FPGA 345 I/O 672FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	鑻辩壒鐖�
绯诲垪	Stratix?
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	閬庢檪鐨�
闆诲-闆绘簮	1.425V?1.575V
宸ヤ綔婧害	0掳C?85掳C(TJ)
鍖呰/绠�	672-BBGA
渚涙噳鍟嗚ō(sh猫)鍌欏寘瑁�	672-FBGA(27x27)
鍩烘湰闆朵欢铏�	EP1S10

鐢�(ch菐n)鍝佸湒鐗�

EP1S10F672C6N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH	鏄�
绗﹀悎姝愮洘RoHS	鏄�
绗﹀悎涓湅RoHS	鏄�
鐙€鎱�(t脿i)	杞�(zhu菐n)鍏�
JESD-30浠ｇ⒓	S-PBGA-B672
JESD-609浠ｇ⒓	1铏�
绺絉AM浣�	920448
CLB鏁�(sh霉)閲�	1200.0
杓稿叆鏁�(sh霉)閲�	426.0
閭忚集鍠厓鏁�(sh霉)	10570.0
杓稿嚭鏁�(sh霉)閲�	426.0
绔瓙鏁�(sh霉)	672
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	1200 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	260
闆绘簮	1.5,1.5 / 3.3
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	3.5姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯欑ū	1.5浼�
鏈€灏忎緵闆婚浕澹�	1.425浼�
鏈€澶ч浕婧愰浕澹�	1.575浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆	鍟嗘キ(y猫)鎿村睍
绲傜瀹屾垚	閷妧閵�
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴︽渶澶у€�(绉�)	40
闀峰害	27.0姣背
瀵害	27.0姣背
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA672,26X26,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	35 X 35 MM锛�1.27 MM闁撹窛锛岀劇閴�锛孊GA-672

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙€鎱�(t脿i)	鐒￠墰
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪)

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10,570鑷�79,040 LE
鏀寔閬犵▼閰嶇疆鏇存柊
澶氶仈7,427,520鍊婻AM浣�(928,440瀛楃瘈(ji茅))鍙敤锛岃€屼笉娓涘皯閭忚集璩囨簮
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