EP1SGX10CF672C6N 鏅�(sh铆)闁擄細2025/4/28 12:12:42 闁辫畝锛�34

EP1SGX10CF672C6N 鏄� Altera 鍏徃锛堢従(xi脿n)宸茶 Intel 鏀惰臣锛夋帹鍑虹殑 Stratix GX 绯诲垪 FPGA 鐨勪竴娆惧瀷铏�(h脿o)銆傝┎鍣ㄤ欢鍩轰簬 90nm 宸ヨ棟鍒堕€狅紝鍏峰倷楂樻€ц兘閭忚集鍠厓鍜岃睈瀵岀殑鏁�(sh霉)瀛椾俊铏�(h脿o)铏曠悊鍔熻兘銆傚叾鍏�(n猫i)閮ㄩ泦鎴愪簡宓屽叆寮忓瓨鍎�(ch菙)鍣�銆侀帠鐩哥挵(hu谩n)锛圥LL锛�銆丩VDS 鎺ュ彛绛夎硣婧愶紝閬╁悎鐢ㄤ簬閫氫俊銆佽▓(j矛)绠椾互鍙婂伐妤�(y猫)鎺у埗绛夐牁(l菒ng)鍩�銆�
銆€銆€Stratix GX 绯诲垪鏄� Altera 閲濆皪(du矛)楂樻€ц兘鎳�(y墨ng)鐢ㄦ帹鍑虹殑閲嶈鐢�(ch菐n)鍝佺窔涔嬩竴锛孍P1SGX10CF672C6N 鍨嬭櫉(h脿o)鍏锋湁 10,430 鍊�(g猫)閭忚集鍠厓锛屾敮鎸� PCIe 鍜� DDR2/DDR3 瀛樺劜(ch菙)鎺ュ彛锛屽苟涓旀彁渚涗簡楂橀€熶覆琛屾敹鐧�(f膩)鍣紙Transceiver锛�锛屾暩(sh霉)鎿�(j霉)鍌宠几閫熺巼鍙仈(d谩) 6.375Gbps銆�

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灏佽锛欶G672
銆€銆€閭忚集鍠厓鏁�(sh霉)锛�10,430
銆€銆€I/O 鏁�(sh霉)閲忥細570
銆€銆€RAM 璩囨簮锛氱磩 835Kb
銆€銆€DSP 妯″鏁�(sh霉)閲忥細120
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€闆绘簮闆诲锛�1.5V 鏍稿績锛�3.3V 閭婄罚 I/O
銆€銆€涓茶鏀剁櫦(f膩)鍣ㄩ€氶亾鏁�(sh霉)锛�12
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