鏅傞枔锛�2025/5/9 15:27:52
闁辫畝锛�33
EP4CGX15BF14C8 鏄竴娆剧敱 Intel锛堝墠韬偤 Altera锛夌敓鐢㈢殑 Cyclone IV GX 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪 FPGA 閲濆皪閫氫俊銆佸伐妤�(y猫)銆佽粛浜嬪拰寤ｆ挱甯傚牬鎻愪緵楂樻�ц兘鍜屼綆鍔熻�楃殑瑙ｆ焙鏂规銆侲P4CGX15BF14C8 鍏锋湁璞愬瘜鐨勬暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 鍔熻兘鍜屽彲绶ㄧ▼閭忚集璩囨簮锛岄仼鐢ㄤ簬闇�瑕佸京闆滄暩(sh霉)鎿�(j霉)铏曠悊鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�瑭插瀷铏熶腑鐨� EP4 琛ㄧず绗洓浠� Cyclone 绯诲垪锛孋GX 琛ㄧず闆嗘垚浜嗘敹鐧�(f膩)鍣ㄧ殑鍔熻兘鐗堟湰锛�15 琛ㄧず澶х磩 1.5 钀�嬮倧杓柈鍏�锛孊F14 琛ㄧず灏佽椤炲瀷鐐� FBGA-256锛孋8 琛ㄧず閫熷害绛夌礆銆�
閭忚集鍠厓锛�14976
銆�銆�鍏ф牳闆诲锛�1.0V
銆�銆�I/O 闆诲锛�1.5V/1.8V/2.5V/3.3V
銆�銆�閰嶇疆瀛樺劜鍣細M4A 鎴� AS
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽锛欶BGA-256
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 3.125 Gbps
銆�銆�RAM锛氱磩 432 Kb
銆�銆�DSP 妯″锛�20 鍊�
銆�銆�鐢ㄦ埗闁冨瓨锛�512 Kb
EP4CGX15BF14C8 鎻愪緵浜嗗挤澶х殑鍙法绋嬮倧杓姛鑳�锛岃兘澶犳豢瓒冲绋京闆滆ō瑷堥渶姹�銆傚叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂樻�ц兘鏀剁櫦(f膩)鍣ㄦ敮鎸侀珮閬� 3.125 Gbps 鐨勪覆琛岄�氫俊閫熺巼锛岄仼鍚堥珮閫熸帴鍙ｆ噳鐢�銆�
銆�銆�2. 鍏х疆 DSP 妯″鍙互鍔犻�熸暩(sh霉)瀛搁亱绠�锛屼緥濡傛烤娉��丗FT 鍜岀煩闄ｄ箻娉曠瓑銆�
銆�銆�3. 鏀寔澶氱ó I/O 妯欐簴锛屽 LVCMOS銆丩VDS 鍜� SSTL锛屽寮蜂簡鑸囧閮ㄨō鍌欑殑鍏煎鎬�銆�
銆�銆�4. 鎻愪緵闈堟椿鐨勬檪閻樼鐞嗛伕闋�锛屽寘鎷� PLL 鍜� DLL锛岀敤浜庣敓鎴愬拰鍒嗛厤绮剧⒑鐨勬檪閻樹俊铏�銆�
銆�銆�5. 宓屽叆寮忓瓨鍎插櫒濉婏紙M9K 鍜� M4K锛夋敮鎸佹繁搴︾珐瀛樺拰 FIFO 瀵︾従(xi脿n)銆�
銆�銆�6. 鏀寔澶氱ó閰嶇疆妯″紡锛屽寘鎷富鍕曚覆琛� (AS) 鍜岃鍕曚覆琛� (PS)锛屼究浜庣郴绲�(t菕ng)闆嗘垚銆�
銆�銆�7. 杓冧綆鐨勫姛鑰楃壒鎬т娇鍏堕仼鐢ㄤ簬灏嶈兘鏁堣姹傝純楂樼殑渚挎敎寮忔垨宓屽叆寮忕郴绲�(t菕ng)銆�
銆�銆�8. 鎻愪緵 JTAG 鎺ュ彛锛岀敤浜庤瑭﹀拰娓│鐩殑銆�
EP4CGX15BF14C8 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)閫氫俊鍜岄浕淇¤ō鍌�锛屽璺敱鍣�銆佷氦鎻涙鍜屽熀绔�銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栨帶鍒�锛屽閬嬪嫊鎺у埗鍣ㄥ拰 PLC銆�
銆�銆�3. 瑕栭牷鍜屽湒鍍忚檿鐞�锛屼緥濡傞珮娓呰闋荤法瑙ｇ⒓鍣ㄥ拰瑕栬妾㈡脯绯荤当(t菕ng)銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌�锛屽瓒呰伈娉㈡巸鎻忓剙鍜岀梾浜虹洠(ji膩n)璀峰剙銆�
銆�銆�5. 杌嶄簨鍜岃埅绌鸿埅澶╅牁鍩燂紝濡傞浄閬旂郴绲�(t菕ng)鍜屽皫鑸ō鍌�銆�
銆�銆�6. 娓│鍜屾脯閲忓剙鍣�锛屼緥濡傜ず娉㈠櫒鍜屼俊铏熺櫦(f膩)鐢熷櫒銆�
銆�銆�7. 浠讳綍闇�瑕侀珮闈堟椿鎬у拰楂樻�ц兘鐨勫祵鍏ュ紡绯荤当(t菕ng)銆�
EP4CGX15BF14C7N, EP4CGX15DF27C7N, EP4CGX15DF27C8N
