EP4SGX360HF35C2G 鏅�(sh铆)闁擄細2025/5/8 0:58:54 闁辫畝锛�25

EP4SGX360HF35C2G 鏄� Altera锛堢従(xi脿n)鐐� Intel FPGA 闆嗗湗(tu谩n)锛夋帹鍑虹殑 Stratix IV GX 绯诲垪 FPGA 鐨勪竴鍊�(g猫)鍏烽珨鍨嬭櫉(h脿o)銆傝┎绯诲垪 FPGA 灏堢偤楂樻€ц兘鍜屼綆鍔熻€楁噳(y墨ng)鐢ㄨō(sh猫)瑷�(j矛)锛岄仼鐢ㄤ簬閫氫俊銆佽▓(j矛)绠�銆佸唬鎾互鍙婅粛浜嬪拰鑸┖鑸ぉ绛夐牁(l菒ng)鍩�銆�
銆€銆€Stratix IV GX 鍩轰簬 40nm 鍒堕€犲伐钘濓紝鎻愪緵浜嗚睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊 (DSP) 妯″銆佸祵鍏ュ紡瀛樺劜(ch菙)鍣ㄤ互鍙婇珮閫熸敹鐧�(f膩)鍣ㄥ姛鑳�銆侲P4SGX360HF35C2G 鍏烽珨闆嗘垚浜嗗閬�(d谩) 36 钀€�(g猫)閭忚集鍠厓锛屽苟鏀寔楂橀仈(d谩) 11.3 Gbps 鐨勪覆琛屾敹鐧�(f膩)鍣ㄩ€熺巼銆�

鍙冩暩(sh霉)

閭忚集鍠厓鏁�(sh霉)閲忥細360K
銆€銆€閰嶇疆闁冨瓨锛氫笉闆嗘垚
銆€銆€I/O 鏁�(sh霉)閲忥細860
銆€銆€鏀剁櫦(f膩)鍣ㄩ€氶亾鏁�(sh霉)锛�36
銆€銆€鏀剁櫦(f膩)鍣ㄩ€熺巼锛�11.3 Gbps
銆€銆€鏈€澶у伐浣滈牷鐜囷細575 MHz
銆€銆€瀛樺劜(ch菙)鍣ㄨ硣婧愶細M9K blocks: 1152, M144K blocks: 72
銆€銆€DSP 妯″鏁�(sh霉)閲忥細720
銆€銆€灏佽椤炲瀷锛欶BGA 1141
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€鍒剁▼宸ヨ棟锛�40nm

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