鏅傞枔锛�2025/6/6 12:56:40
闁辫畝锛�8
MT18N101K101CT鏄竴娆鹃珮鎬ц兘鐨凞DR3L SDRAM鍏у瓨鑺墖锛屼富瑕佺敤浜庣Щ鍕曡ō鍌�銆佸祵鍏ュ紡绯荤当(t菕ng)浠ュ強鍏朵粬灏嶄綆鍔熻�楀拰楂樺付瀵湁瑕佹眰鐨勬噳鐢ㄥ牬鏅�銆傝┎鑺墖鐢盡icron Technology锛堢編鍏夌鎶�锛夌敓鐢�(ch菐n)锛岄噰鐢ㄥ厛閫茬殑鍒堕�犲伐钘�锛屽叿鍌欎綆鍔熻�楀拰楂樺彲闈犳�х殑鐗归粸銆�
銆�銆�DDR3L鏄疍DR3鐨勪綆闆诲鐗堟湰锛屽伐浣滈浕澹撶偤1.35V锛岀浉姣旀婧朌DR3鐨�1.5V鑳藉椤憲闄嶄綆鍔熻��锛岄潪甯搁仼鍚堥浕姹犱緵闆荤殑渚挎敎寮忚ō鍌欍�傛鑺墖鍏锋湁鍑鸿壊鐨勬�ц兘鍜屽閲�锛屾敮鎸佸揩閫熺殑鏁�(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
瀹归噺锛�1Gb锛�128Mb x 8锛�
銆�銆�鎺ュ彛椤炲瀷锛欴DR3L
銆�銆�宸ヤ綔闆诲锛�1.35V
銆�銆�鏁�(sh霉)鎿�(j霉)閫熺巼锛�800Mbps~1600Mbps
銆�銆�灏佽褰㈠紡锛欶BGA 78-ball
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C ~ +85掳C
銆�銆�I/O妯欐簴锛歋STL-15
銆�銆�寮曡叧閰嶇疆锛�78-ball FBGA
1. 浣庡伐浣滈浕澹�1.35V锛屾湁鏁堥檷浣庡姛鑰�銆�
銆�銆�2. 鏀寔楂橀仈1600Mbps鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛屾豢瓒抽珮閫熸暩(sh霉)鎿�(j霉)铏曠悊闇�姹�銆�
銆�銆�3. 鍏峰倷On-Die Termination锛圤DT锛夊姛鑳斤紝鍎�(y艒u)鍖栦俊铏熷畬鏁存��銆�
銆�銆�4. 鍏х疆婧害瑁滃劅鑷埛鏂帮紙Temperature Compensated Self-Refresh锛孴CSR锛�锛屽湪涓嶅悓婧害涓嬩繚鎸佹暩(sh霉)鎿�(j霉)绌�(w臎n)瀹氭��銆�
銆�銆�5. 鏀寔Partial Array Self-Refresh锛圥ASR锛夋ā寮忥紝閫蹭竴姝ラ檷浣庡緟姗熷姛鑰�銆�
銆�銆�6. 楂樺彲闈犳�цō瑷�锛岄仼鐢ㄤ簬鍤磋嫑鐠�(hu谩n)澧冧笅鐨勬噳鐢�銆�
銆�銆�7. 绗﹀悎RoHS妯欐簴锛岀挵(hu谩n)淇濈劇閴涘皝瑁�銆�
MT18N101K101CT寤ｆ硾鎳夌敤浜庡悇椤為渶瑕侀珮鏁堣兘鍜屼綆鍔熻�楀瓨鍎茬殑闋樺煙锛�
銆�銆�1. 鏅鸿兘鎵嬫鍜屽钩鏉块浕鑵︾瓑绉诲嫊瑷倷銆�
銆�銆�2. 宓屽叆寮忕郴绲�(t菕ng)锛屽宸ユキ(y猫)鎺у埗銆侀啱(y墨)鐧傝ō鍌欍�佺恫(w菐ng)绲￠�氫俊瑷倷銆�
銆�銆�3. 鍙┛鎴磋ō鍌欏拰鍏朵粬渚挎敎寮忛浕瀛愮敘(ch菐n)鍝�銆�
銆�銆�4. 鏁�(sh霉)瀛楅浕瑕�銆佹闋傜洅鍙婂叾浠栨秷璨婚闆诲瓙鐢�(ch菐n)鍝併��
銆�銆�5. 鐗╄伅(li谩n)缍�(w菐ng)锛圛oT锛夎ō鍌欏強閭婄罚瑷堢畻骞宠嚭銆�
MT18N101K101BT, MT18N101K101D
