銆�銆�鈼�鏍稿績:ARM?32浣�Cortex?-M3 CPU

銆�銆�鈼�鏈�澶ч牷鐜�72 MHz锛屽湪0绛夊緟鐙�鎱�(t脿i)鍏�(n猫i)瀛樿í鍟忔檪1.25 DMIPS/MHz (Dhrystone 2.1)鎬ц兘

銆�銆�鈼�鍠�鍛ㄦ湡涔樻硶鍜岀‖浠跺妰鍒�

銆�銆�鈼�瑷樻喍

銆�銆�鈼�64鍒�256kbytes鐨勯杻瀛�

銆�銆�鈼�64kbytes閫氱敤SRAM

銆�銆�鈼�鏅傞悩銆侀噸缃�鍜屼緵鎳�(y墨ng)绠＄悊

銆�銆�鈼�2.0鑷�3.6 V鎳�(y墨ng)鐢ㄩ浕婧愬拰I/ o

銆�銆�鈼�POR, PDR鍜屽彲绶ㄧ▼闆诲�撴�㈡脯鍣�(PVD)

銆�銆�鈼�3- 25 MHz鏅堕珨鎸�钑╁��

銆�銆�鈼�鍏�(n猫i)閮�8鍏嗚但宸ュ粻淇�鍓�RC

銆�銆�鈼�鍏�(n猫i)閮�40khz RC甯舵牎婧�(zh菙n)

銆�銆�鈼�鐢ㄤ簬鏍℃簴(zh菙n)RTC鐨�32 kHz鎸�钑╁��

銆�銆�鈼�浣庡姛鐜�

銆�銆�鈼�鐫＄湢銆佸仠姝㈠拰寰呮��(j墨)妯″紡

銆�銆�鈼�RTC鍜屽倷浠藉瘎瀛樺櫒鐨�VBAT渚涙噳(y墨ng)

銆�銆�鈼�2 脳 12浣�锛�1 渭s A/D杞�(zhu菐n)鎻涘櫒(16閫氶亾)

銆�銆�鈼�杞�(zhu菐n)鎻涜寖鍦�:0 ~ 3.6 V

銆�銆�鈼�閲囨ǎ鍜屼繚鎸佽兘鍔�

銆�銆�鈼�婧�搴﹀偝鎰熷��

銆�銆�鈼�浜ら尟妯″紡涓嬫渶澶�2鍊�MSPS

銆�銆�鈼�2 脳 12浣�D/A杞�(zhu菐n)鎻涘櫒

銆�銆�鈼�DMA: 12閫氶亾DMA鎺у埗鍣�

銆�銆�鈼�鏀�鎸佺殑澶栧湇瑷�(sh猫)鍌�:瀹氭檪鍣�銆�adc銆�DAC銆�I2Ss銆�spi銆�i2c鍜�usart

銆�銆�鈼�瑾�(di脿o)瑭︽ā寮�

銆�銆�鈼�涓茶�岀窔璺�瑾�(di脿o)瑭�(SWD)鍜�JTAG鎺ュ彛

銆�銆�鈼�Cortex?-M3 Embedded Trace Macrocell?

銆�銆�鈼�澶氶仈(d谩)80鍊嬪揩閫�I/O绔�鍙�

銆�銆�鈼�51/80鍊�I/ o锛屾墍鏈�I/ o閮藉彲浠ユ槧灏勫埌16鍊嬪�栭儴涓�鏂峰悜閲忎笂锛屽咕涔庢墍鏈�I/ o閮借兘鏀�鎸�5鍊�v

銆�銆�鈼�CRC瑷堢畻鍠�鍏�锛�96浣嶅敮涓�ID

銆�銆�鈼�澶氶仈(d谩)10鍊嬭▓鏅傚櫒锛屽叿鏈夐嚌灏栭噸鏄犲皠鍔熻兘

銆�銆�鈼�鏈�澶�4鍊�16浣嶅畾鏅傚櫒锛屾瘡鍊嬪畾鏅傚櫒鏈�澶�4鍊�IC/OC/PWM鎴栬剤娌栬▓鏁�(sh霉)鍣ㄥ拰姝ｄ氦(澧為噺)绶ㄧ⒓鍣ㄨ几鍏�

銆�銆�鈼�1 脳 16浣嶉浕姗�(j墨)鎺у埗PWM瀹氭檪鍣�锛屽叿鏈夋�绘檪鐢�(ch菐n)鐢熷拰绶婃�ュ仠姝㈠姛鑳�

銆�銆�鈼�2 脳鐪嬮杸鐙楀畾鏅傚櫒(鐛�(d煤)绔嬪拰绐楀彛)

銆�銆�鈼�SysTick瀹氭檪鍣�:24浣嶄笅琛岃▓鏁�(sh霉)鍣�

銆�銆�鈼�2 脳 16浣嶅熀鏈�瀹氭檪鍣ㄩ��(q奴)鍕�DAC

銆�銆�鈼�澶氶仈(d谩)14鍊嬮�氫俊鎺ュ彛锛屽叿鏈夊紩鑵抽噸鏄犲皠鍔熻兘

銆�銆�鈼�澶氶仈(d谩)2 脳 I2C鎺ュ彛(SMBus/PMBus)

銆�銆�鈼�鏈�澶�5鍊�USARTs (ISO 7816鎺ュ彛锛�LIN, IrDA鍔熻兘锛岃��(di脿o)鍒惰В瑾�(di脿o)鍣ㄦ帶鍒�)

銆�銆�鈼�鏈�澶�3鍊�spi (18mbit /s)锛� 2鍊嬪叿鏈夊�氳��I2S鎺ュ彛锛岄�氶亷鍏堥��(j矛n)鐨勯帠鐩哥挵(hu谩n)鏂规�堟彁渚涢煶闋婚�炵簿搴�

銆�銆�鈼�2 脳 CAN鎺ュ彛(2.0B娲诲嫊)锛�512瀛楃瘈(ji茅)灏堢敤SRAM

銆�銆�鈼�USB 2.0鍏ㄩ�熻ō(sh猫)鍌�/涓绘��(j墨)/OTG鎺у埗鍣�锛屽付鐗囦笂PHY锛屾敮鎸�HNP/SRP/ID锛屽叿鏈�1.25 Kbytes灏堢敤SRAM

銆�銆�鈼�10/100浠ュお缍�(w菐ng)MAC甯跺皥鐢ㄧ殑DMA鍜�SRAM (4kbytes):鏀�鎸�IEEE1588纭�浠�锛屾墍鏈夊寘閮芥敮鎸�MII/RMII