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鍏�(n猫i)鏍革細ARM Cortex-M0+
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銆€銆€Flash瀛樺劜(ch菙)鍣細64KB
銆€銆€SRAM锛�8KB
銆€銆€闆诲鑼冨湇锛�1.65V~3.6V
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銆€銆€I/O鑰愬锛�5V
銆€銆€灏佽褰㈠紡锛歀QFP64
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STM32L051T6Y6鍏峰倷浠ヤ笅涓昏鐗规€э細
銆€銆€1. 楂樻晥鐨凙RM Cortex-M0+鍏�(n猫i)鏍�锛屽叿鏈塗humb-2鎸囦护闆�锛屾彁渚涘崜瓒婄殑浠ｇ⒓瀵嗗害鍜屾€ц兘銆�
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銆€銆€7. 鎻愪緵澶氶仈(d谩)49鍊�(g猫)GPIO寮曡叧锛屾敮鎸佸绋京(f霉)鐢ㄥ姛鑳�锛屼究浜庨潏娲婚厤缃�銆�
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STM32L051T6Y6寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
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