鍨嬭櫉(h脿o)锛歑A7A50T-1CSG324Q
銆�銆�灏佽�濆舰寮忥細CSG (CSP)
銆�銆�寮曡叧鏁�(sh霉)锛�324
銆�銆�FPGA 绯诲垪锛欰rtix-7
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master Parallel, etc.
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 50K
銆�銆�鍏�(n猫i)閮� RAM锛氱磩 2.4MB
銆�銆�DSP Slice 鏁�(sh霉)閲忥細240
銆�銆�I/O Bank 鏁�(sh霉)閲忥細16
銆�銆�鏈�澶х敤鎴� I/O 鏁�(sh霉)閲忥細240

XA7A50T-1CSG324Q 鍏锋湁浠ヤ笅涓昏�佺壒鎬э細
銆�銆�1. 楂樻�ц兘鑸囦綆鍔熻�楋細閲囩敤 28nm 宸ヨ棟鎶�琛�(sh霉)锛屽湪淇濊瓑鎬ц兘鐨勫悓鏅�(sh铆)澶у箙闄嶄綆鍔熻�椼��
銆�銆�2. 璞愬瘜鐨勯倧杓�璩囨簮锛氭彁渚涘ぇ绱� 50K 鐨勯倧杓�鍠�鍏�锛屾豢瓒充腑灏忓瀷瑷�(sh猫)瑷�(j矛)闇�姹傘��
銆�銆�3. 鍏�(n猫i)宓� DSP 妯″�婏細鍏�(n猫i)缃� 240 鍊�(g猫) DSP Slice锛岄仼鍚堝��(sh铆)鐝�(xi脿n)寰�(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏�(h脿o)铏曠悊绠楁硶銆�
銆�銆�4. 澶у�归�� Block RAM锛氱附?c猫)钀樿�僺鐐� 2.4MB锛屽彲閰嶇疆鐐� FIFO銆丷AM 鎴� ROM锛岀敤浜庢暩(sh霉)鎿�(j霉)瀛樺劜(ch菙)鍜岃檿鐞嗐��
銆�銆�5. 楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛氭敮鎸侀珮閬�(d谩) 6.6Gbps 鐨� GTX 鏀剁櫦(f膩)鍣�锛岄仼閰嶅�氱ó楂橀�熸帴鍙ｅ崝(xi茅)璀�3.0銆�
銆�銆�6. 鍙�绶ㄧ▼鏅�(sh铆)閻樼�＄悊锛氬��(n猫i)鍚� PLL 鍜� MMCM锛岃兘澶犵敓鎴愮簿纰虹殑鏅�(sh铆)閻橀牷鐜囦互閬╂噳(y墨ng)涓嶅悓鐨勬噳(y墨ng)鐢ㄩ渶姹傘��
銆�銆�7. 鏀�鎸佸�氱ó閰嶇疆妯″紡锛氬寘鎷� Slave Serial銆丮aster Parallel 绛夋柟寮忥紝渚夸簬闈堟椿鍔犺級绋嬪簭銆�
銆�銆�8. 寤ｆ硾鐨勫伐浣滄韩搴﹁寖鍦嶏細寰� -40掳C 鍒� +100掳C锛岀⒑淇濆湪妤电��鐠�(hu谩n)澧冧笅鐨勫彲闈犳��銆�
銆�銆�9. 灏忓瀷鍖栧皝瑁濓細CSG324 灏佽�濆舰寮忕瘈(ji茅)鐪� PCB 绌洪枔锛岀壒鍒ラ仼鍚堢穵婀婂瀷瑷�(sh猫)瑷�(j矛)銆�

XA7A50T-1CSG324Q 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宓屽叆寮忚�栬�虹郴绲�(t菕ng)锛氬�傛��(j墨)鍣ㄨ�栬�虹浉姗�(j墨)銆佸湒鍍忚檿鐞嗚ō(sh猫)鍌欑瓑锛屽埄鐢ㄥ叾寮�(qi谩ng)澶х殑骞惰�岃��(j矛)绠楄兘鍔涘拰浣庡欢閬茬壒榛�(di菐n)銆�
銆�銆�2. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栵細鐢ㄤ簬閬�(y霉n)鍕�(d貌ng)鎺у埗銆丳LC 绶ㄧ▼銆佸伐妤�(y猫)缍�(w菐ng)绲�(lu貌)閫氫俊绛夐牁(l菒ng)鍩燂紝鍥犲叾鍏峰倷楂樺彲闈犳�у拰瀵�(sh铆)鏅�(sh铆)闊挎噳(y墨ng)鑳藉姏銆�
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