XC4VLX15-10SFG363C 鏅傞枔锛�2022/11/5 16:43:17 闁辫畝锛�813

鐢�(ch菐n)鍝佸瀷铏� XC4VLX15-10SFG363C鎻忚堪IC FPGA 240 I/O 363FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)

姒傝堪

鐢�(ch菐n)鍝佸瀷铏� XC4VLX15-10SFG363C鎻忚堪IC FPGA 240 I/O 363FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)鐢熺敘(ch菐n)寤犲Xilinx鍏徃绯诲垪Virtex?-4 LX閮ㄥ垎鐙€鎱�(t脿i)娲绘€ч浕澹�-闆绘簮1.14V~1.26V宸ヤ綔婧害0掳C~85掳C(TJ)鍖�/绠�363-FBGA锛孎(xi脿n)CBGA渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘363-FCBGA(17x17)鍩虹(ch菙)閮ㄤ欢铏� XC4VLX15

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楂樻€ц兘閭忚集鎳�(y墨ng)鐢ㄨВ姹烘柟妗�

Xesium鏅傞悩鎶€琛�(sh霉)

鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)濉�

闄勫姞鐨勭浉浣嶅尮閰嶆檪閻樺垎闋诲櫒(PMCD)

宸垎鍏ㄧ悆鏅傞悩

XtremeDSP鍒囩墖

18 x 18锛屼簩閫�(j矛n)鍒惰(b菙)纰�锛屽付绗﹁櫉涔樻暩(sh霉)

鍙伕鐨勭閬撻殠娈�

鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�

鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

鍒嗗竷寮廟AM

闆欑鍙�18-Kbit RAM妯″路鍙伕娴佹按绶氱礆路鍙伕鐨勫彲绶ㄧ▼FIFO閭忚集鑷嫊灏嘡AM淇¤櫉閲嶆柊鏄犲皠鐐篎IFO淇¤櫉

楂橀€熷瓨鍎插櫒鎺ュ彛鏀寔DDR鍜孌DR-2 SDRAM锛孮DR-II鍜孯LDRAM-II

SelectIO鎶€琛�(sh霉)

1.5V鑷�3.3VI / O鎿嶄綔

鍏�(n猫i)缃瓹hipSync婧愬悓姝ユ妧琛�(sh霉)

鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜

绮剧窗(x矛)鐨処 / O閵€琛屾キ(y猫)鍕�(w霉)(鍦ㄤ竴瀹堕妧琛岄厤缃�)

闈堟椿鐨勯倧杓硣婧�

瀹夊叏鑺墖AES姣旂壒娴佸姞瀵�

90 nm閵匔MOS宸ヨ棟

1.2V鏍稿績闆诲

鍊掕鑺墖灏佽鍖呮嫭鐒￠墰灏佽閬告搰

鍙冩暩(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)	鏄�
绗﹀悎姝愮洘RoHS妯�(bi膩o)婧�(zh菙n)	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏅傞悩闋荤巼-鏈€澶у€�	1028.0 MHz
JESD-30浠ｇ⒓	S-PBGA-B363
JESD-609浠ｇ⒓	E1
绺絉AM浣嶆暩(sh霉)	884736
CLB鏁�(sh霉)閲�	1536.0
杓稿叆鏁�(sh霉)閲�	240.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	13824.0
杓稿嚭鏁�(sh霉)閲�	240.0
绲傜鏁�(sh霉)閲�	363
宸ヤ綔婧害-鏈€灏忓€�	0鈩�
宸ヤ綔婧害-鏈€楂�	85鈩�
绲勭箶	1536 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	260
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂樺害-鏈€澶�	1.99姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲	1.2 V
闆绘簮闆诲-鏈€灏忓€�	1.14 V
闆绘簮闆诲-鏈€澶у€�	1.26 V
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	0.8姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴�-鏈€澶у€�	涓夊崄
闀峰害	17.0姣背
瀵害	17.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰９浠ｇ⒓	FBGA
鍖呯瓑鍍逛唬纰�	BGA363,20X20,32
鍖呰褰㈢媭	寤ｅ牬
鍖呰棰�(f膿ng)鏍�	缍�(w菐ng)鏍奸櫍鍒�锛岀簿绱�(x矛)闁撹窛
鍒堕€犲晢鍖呰瑾槑	鐒￠墰锛孎(xi脿n)BGA-363