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    椤炲垾锛氶泦鎴愰浕璺� (IC)
    瀹跺涵锛氬祵鍏ュ紡 - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛�
    绯诲垪锛歏irtex?-4

姒傝堪

    椤炲垾锛氶泦鎴愰浕璺� (IC)
    瀹跺涵锛氬祵鍏ュ紡 - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛�
    绯诲垪锛歏irtex?-4
    杓稿叆/杓稿嚭鏁�(sh霉)锛�448
    閭忚集濉�/鍏冧欢鏁�(sh霉)锛�59904
    闁€鏁�(sh霉)锛�-
    闆绘簮闆诲锛�1.14 V ~ 3.45 V
    瀹夎椤炲瀷锛氳〃闈㈣布瑁�
    宸ヤ綔婧害锛�0掳C ~ 85掳C
    灏佽/澶栨锛�668-FCBGA
    渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細*
    鍏跺畠鍚嶇ū锛�122-1494

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楂樻€ц兘閭忚集鎳�(y墨ng)鐢ㄨВ姹烘柟妗�

Xesium鏅傞悩鎶€琛�(sh霉)

鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)妯″

闄勫姞鐨勭浉浣嶅尮閰嶆檪閻樺垎闋诲櫒(PMCD)

宸垎鍏ㄥ眬鏅傞悩

XtremeDSPSlice

18 x 18锛屼簩閫插埗瑁滅⒓锛屽付绗﹁櫉涔樻硶鍣�

鍙伕鐨勭閬撻殠娈�

鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�

鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

鍒嗗竷寮廟AM

闆欑鍙�18 Kbit RAM濉娐峰彲閬哥殑绠＄窔绱毬峰彲閬哥殑鍙法绋婩IFO閭忚集鑷嫊灏嘡AM淇¤櫉閲嶆柊鏄犲皠鐐篎IFO淇¤櫉

楂橀€熷瓨鍎插櫒鎺ュ彛鏀寔DDR鍜孌DR-2 SDRAM锛孮DR-II鍜孯LDRAM-II

SelectIO鎶€琛�(sh霉)

1.5V鑷�3.3VI / O鎿嶄綔

鍏�(n猫i)缃瓹hipSync婧愬悓姝ユ妧琛�(sh霉)

鏁�(sh霉)鎺ч樆鎶�(DCI)鏈夋簮绲傜

绱�(x矛)绮掑害鐨処 / O閵€琛屾キ(y猫)鍕�(w霉)(鍦ㄤ竴鍊嬮妧琛屼腑閫茶閰嶇疆)

闈堟椿鐨勯倧杓硣婧�

瀹夊叏鑺墖AES浣嶆祦鍔犲瘑

90 nm閵匔MOS宸ヨ棟

1.2V鏍稿績闆诲

鍊掕鑺墖灏佽锛屽寘鎷劇閴涘皝瑁濋伕鎿�

鍙冩暩(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH	鏄�
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏈€澶ф檪閻橀牷鐜�	1028.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B668
JESD-609浠ｇ⒓	1铏�
绺絉AM浣�	2949120
CLB鏁�(sh霉)閲�	6656.0
杓稿叆鏁�(sh霉)閲�	448.0
閭忚集鍠厓鏁�(sh霉)	59904.0
杓稿嚭鏁�(sh霉)閲�	448.0
绔瓙鏁�(sh霉)	668
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	6656 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	2.85姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.2浼�
鏈€灏忎緵闆婚浕澹�	1.14浼�
鏈€澶ч浕婧愰浕澹�	1.26浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴︽渶澶у€�(绉�)	30
闀峰害	27.0姣背
瀵害	27.0姣背
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA668,26X26,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	鐒￠墰FBGA-668