XC4VSX55-10FF1148I 鏅�(sh铆)闁擄細2023/7/11 14:29:35 闁辫畝锛�774

鎻忚堪

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鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸湒鐗�

XC4VSX55-10FF1148I

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鐢�(ch菐n)鍝佺ó椤�	FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绯诲垪	XC4VSX55
闆朵欢鐙€鎱�(t脿i)	娲绘€�
绺絉AM浣�	5898240
閭忚集鍏冧欢鏁�(sh霉)閲�	55296 LE
鑷仼鎳�(y墨ng)閭忚集妯″ - ALM	24576 ALM
宓屽叆寮忓収(n猫i)瀛�	5.63 Mbit
杓稿叆/杓稿嚭绔暩(sh霉)閲�	640 I/O
宸ヤ綔闆绘簮闆诲	1.2 V
鏈€灏忓伐浣滄韩搴�	- 40鈩�
鏈€澶у伐浣滄韩搴�	+ 100鈩�
鍒嗗竷寮廟AM	384 kbit
鍏�(n猫i)宓屽紡濉奟AM - EBR	5760 kbit
鏈€澶у伐浣滈牷鐜�	500 MHz
閭忚集鏁�(sh霉)绲勫鏁�(sh霉)閲忊€斺€擫AB	6144 LAB
瀹夎椤炲瀷	琛ㄩ潰璨艰
灏佽 / 绠遍珨	FCBGA-1148

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

RoHS鐙€鎱�(t脿i)	绗﹀悎RoHS瑕�(gu墨)瀹�
姘村垎鏁忔劅鎬ф按骞�(MSL)	4(72灏忔檪(sh铆))

鐗归粸(di菐n)

鈼廣irtex-4SX锛氱敤浜庢暩(sh霉)瀛椾俊铏熻檿鐞�(DSP)鎳�(y墨ng)鐢ㄧ殑楂樻€ц兘瑙ｆ焙鏂规

鈼廥esium?鏅�(sh铆)閻樻妧琛�(sh霉)

鏁�(sh霉)瀛楁檪(sh铆)閻樼鐞嗗櫒(DCM)妯″

闄勫姞鐩镐綅鍖归厤鏅�(sh铆)閻樺垎闋诲櫒(PMCD)

宸垎鍏ㄥ眬鏅�(sh铆)閻�

鈼廥tremeDSP?Slice

18x18锛屼簩閫�(j矛n)鍒惰(b菙)纰�锛屽付绗﹁櫉涔樻硶鍣�

鍙伕鐨勭閬撻殠娈�

鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�

鈼忔櫤鑳絉AM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

鍒嗗竷寮廟AM

闆欑鍙�18KbRAM濉娐峰彲閬哥殑绠＄窔绱毬峰彲閬哥殑鍙法绋婩IFO閭忚集鑷嫊灏嘡AM淇¤櫉閲嶆柊鏄犲皠鐐篎IFO淇¤櫉

楂橀€熷瓨鍎插櫒鎺ュ彛鏀寔DDR鍜孌DR-2SDRAM锛孮DR-II鍜孯LDRAM-II銆�

鈼廠electIO?鎶€琛�(sh霉)

1.5V鑷�3.3VI/O鎿嶄綔

鍏�(n猫i)缃瓹hipSync?婧愬悓姝ユ妧琛�(sh霉)

鏁�(sh霉)鎺ч樆鎶�(DCI)鏈夋簮绲傜

绱�(x矛)绮掑害鐨処/O閵€琛屾キ(y猫)鍕�(w霉)(鍦ㄤ竴鍊�(g猫)閵€琛屼腑閫�(j矛n)琛岄厤缃�)

鈼忛潏娲荤殑閭忚集璩囨簮

鈼忓畨鍏ㄨ姱鐗嘇ES浣嶆祦鍔犲瘑

鈼�90nm閵匔MOS宸ヨ棟

鈼�1.2V鏍稿績闆诲

鈼忓€掕鑺墖灏佽锛屽寘鎷劇閴涘皝瑁濋伕鎿�

CAD妯″瀷

XC4VSX55-10FF1148I绗﹁櫉

XC4VSX55-10FF1148I鑵冲嵃

灏佽

XC4VSX55-10FF1148I灏佽

鏇夸唬鍨嬭櫉

鍨嬭櫉	鍒堕€犲晢	鍝佸悕	鎻忚堪
XC4VSX55-10FFG1148C	璩介潏鎬�	FPGA鑺墖	55296Cells 90nm(CMOS) Technology 1.2V 1148Pin FCBGA
XC4VSX55-11FF1148C	璩介潏鎬�	FPGA鑺墖	55296Cells 90nm Technology 1.2V 1148Pin FCBGA
XC4VSX55-11FFG1148I	璩介潏鎬�	FPGA鑺墖	55296 Cells 90nm Technology 1.2V 1148Pin FCBGA