鏅傞枔锛�2025/5/10 9:51:25
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XC5VLX330-2FF1760I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗囦腑鐨勪竴鍊嬪瀷铏�銆傝┎绯诲垪 FPGA 閲囩敤鍏堥�茬殑 65nm 宸ヨ棟鍒堕�狅紝鍏锋湁楂樻�ц兘銆侀珮瀵嗗害鍜屼綆鍔熻�楃殑鐗归粸銆俋C5VLX330 鏄� Virtex-5 LX 绯诲垪涓殑涓�鍝�锛屼富瑕侀潰鍚戦�氫俊銆佷俊铏熻檿鐞嗐�佸湒鍍忚檿鐞嗙瓑闋樺煙鎳夌敤銆傝┎鍣ㄤ欢鏀寔璞愬瘜鐨� I/O 妯欐簴鍜岄珮閫熶覆琛屾帴鍙ｏ紝鍚屾檪鍏峰倷闈堟椿鐨勯倧杓硣婧愬拰宓屽叆寮� DSP 妯″銆�
銆�銆�XC5VLX330 鐨� FF1760 灏佽褰㈠紡鎻愪緵澶ч噺鐨勫紩鑵充互婊胯冻寰╅洔鐨勪簰閫ｉ渶姹�锛岃�� '-2' 琛ㄧず鍏堕�熷害绛夌礆銆�
鍨嬭櫉锛歑C5VLX330-2FF1760I
銆�銆�绯诲垪锛歏irtex-5 LX
銆�銆�宸ヨ棟锛�65nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 330,000 鍊�
銆�銆�閰嶇疆瀛樺劜鍣細Block RAM (绱� 9MB)40
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�1760
銆�銆�宸ヤ綔婧害鑼冨湇锛氬伐妤�(y猫)绱� (-40掳C 鑷� +85掳C0V
銆�銆�I/O 闆诲锛�1.8V / 2.5V / 3.3V
銆�銆�閫熷害绛夌礆锛�-2
XC5VLX330-2FF1760I 鎻愪緵浜嗘サ楂樼殑閭忚集瀵嗗害鍜岃睈瀵岀殑鍔熻兘妯″锛岄仼鐢ㄤ簬澶氱ó寰╅洔瑷▓鍫存櫙銆傚畠鍖呭惈澶ч噺鍙法绋嬮倧杓柈鍏冧互鍙婂皥鐢ㄧ殑寰╅洔鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕欍��
銆�銆�姝ゅ锛岃┎ FPGA 鏀寔澶氶仈 24 鍊� RocketIO GTX 鏀剁櫦(f膩)鍣�锛岄�欎簺鏀剁櫦(f膩)鍣ㄨ兘澶犱互楂橀仈 6.5Gbps 鐨勯�熺巼閬嬭锛岄潪甯搁仼鍚堥渶瑕侀珮閫熸暩(sh霉)鎿�(j霉)鍌宠几?sh霉)鑶筋��?锛屼緥濡傚厜绾栭�氫俊鎴栬儗鏉夸簰閫�銆�
銆�銆�鍦ㄥ瓨鍎叉柟闈紝XC5VLX330 閰嶅倷浜嗗ぇ閲忕殑 Block RAM 鍜屽垎甯冨紡 RAM 璩囨簮锛屼娇寰楃敤鎴跺彲浠ュ湪鐗囧収(n猫i)瀵︾従(xi脿n)澶у閲忔暩(sh霉)鎿�(j霉)绶╂矕鎴� FIFO 鍔熻兘銆傚悓鏅傦紝鍏跺璺檪閻樼鐞嗗櫒锛圖CM 鍜� PLL锛夋彁渚涗簡闈堟椿鐨勬檪閻樺垎闋�銆佸�嶉牷鍙婄浉绉昏兘鍔涳紝鏂逛究閫茶绮剧⒑鐨勬檪閻樻帶鍒�銆�
銆�銆�瑭茶姱鐗囬倓鏀寔澶氱ó妯欐簴閰嶇疆妯″紡锛屽寘鎷緸 PROM銆丗lash 鎴栧叾浠栧閮ㄨō鍌欏姞杓夐厤缃暩(sh霉)鎿�(j霉)锛岀⒑淇濊ō瑷堥潏娲绘��銆�
銆�銆�鏈�鍚�锛屽緱鐩婁簬 Xilinx 鐨勬垚鐔熼枊鐧�(f膩)宸ュ叿閺堬紙濡� ISE Design Suite锛�锛岄枊鐧�(f膩)鑰呭彲浠ヤ究鎹峰湴瀹屾垚瑷▓杓稿叆銆佺稖鍚�銆佸竷灞�甯冪窔鍙婇璀夌瓑鍏ㄦ祦绋嬫搷浣�銆�
XC5VLX330-2FF1760I 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鎬ц兘瑷堢畻鍜屽ぇ瑕�(gu墨)妯℃暩(sh霉)瀛楅浕璺殑瑷▓闋樺煙銆傚吀鍨嬫噳鐢ㄥ牬鏅寘鎷細
銆�銆�1. 閫氫俊鍩虹瑷柦 - 濡傜劇绶氬熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鍗�(xi茅)璀拌檿鐞嗚垏鏁�(sh霉)鎿�(j霉)鍖呰綁鐧�(f膩)銆�
銆�銆�2. 楂橀�熶俊铏熻檿鐞� - 鍖呮嫭闆烽仈绯荤当(t菕ng)銆佽粺浠跺畾缇╃劇绶氶浕锛圫DR锛変互鍙婅闋荤法纰艰В纰�銆�
銆�銆�3. 鍦栧儚铏曠悊 - 濡傞啱(y墨)鐧傛垚鍍忚ō鍌欎腑鐨勫鏅傚湒鍍忓寮疯垏鍒嗘瀽銆�
銆�銆�4. 娓│娓噺 - 鎻愪緵闈堟椿鐨勬暩(sh霉)鎿�(j霉)閲囬泦鑸囧垎鏋愬钩鑷�銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖� - 瀵︾従(xi脿n)寰╅洔鐨勯亱鍕曟帶鍒剁畻娉曟垨姗熷櫒瑕栬瑙ｆ焙鏂规銆�
銆�銆�鐢变簬鍏堕珮搴﹀彲绶ㄧ▼鎬�锛孹C5VLX330 閭勫彲鐢ㄤ簬鍘熷瀷闁嬬櫦(f膩)鍜屽畾鍒� ASIC 瑷▓涔嬪墠鐨勯璀夐殠娈�銆�
XC5VLX330T-2FF1760I
銆�銆�XC5VLX330-3FF1760I
