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鑺墖鍨嬭櫉锛歑C5VLX50-3FFG676I
銆€銆€宸ヨ棟鍒剁▼锛�65nm
銆€銆€FPGA 绯诲垪锛歏irtex-5
銆€銆€瀛愮郴鍒楋細LX (Low-Cost)
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 50,000
銆€銆€Block RAM锛�24 MB
銆€銆€DSP Slice 鏁�(sh霉)閲忥細192
銆€銆€閰嶇疆妯″紡锛歋electMAP 鍜� Master/Slave Serial
銆€銆€I/O 閵€琛屾暩(sh霉)锛�28
銆€銆€宸ヤ綔婧害鑼冨湇锛氬伐妤�(y猫)绱氾紙-40掳C 鑷� +100掳C锛�
銆€銆€灏佽椤炲瀷锛欶FG676
銆€銆€閫熷害绛夌礆锛�-3

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XC5VLX50-3FFG676I 鐨勪富瑕佺壒鎬у寘鎷細
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