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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC6SLX75-2CSG484C

XC6SLX75-2CSG484C 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/6/3 10:12:03 鏌ョ湅 闁辫畝锛�11

XC6SLX75-2CSG484C 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪涓殑涓�娆� FPGA 鑺墖銆傝┎绯诲垪鑺墖涓昏闈㈠悜涓綆绔噳(y墨ng)鐢ㄥ競鍫�锛屾彁渚涢珮鎬ц兘銆佷綆鍔熻�楀拰闈堟椿鐨勫彲绶ㄧ▼閭忚集璩囨簮銆�
銆�銆�XC6SLX75 灞簬 Spartan-6 LX 鍣ㄤ欢瀹舵棌锛岄噰鐢� 45nm 宸ヨ棟鍒堕��锛屽叿鏈夎睈瀵岀殑閭忚集鍠厓銆佸 RAM 鍜� DSP Slice 绛夎硣婧�锛岄仼鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆佽闋昏檿鐞嗙瓑澶氱ó鎳�(y墨ng)鐢ㄥ牬鏅��

鍙冩暩(sh霉)

鍨嬭櫉锛歑C6SLX75-2CSG484C
銆�銆�灏佽锛欳SG484
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細75000
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銆�銆�RAM 鏁�(sh霉)閲忥細516KB
銆�銆�DSP Slice 鏁�(sh霉)閲忥細160
銆�銆�I/O 鏁�(sh霉)閲忥細336
銆�銆�宸ヤ綔闆诲锛�1.2V 鏍稿績锛�1.5V/1.8V/2.5V/3.3V I/O
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 70掳C锛夋垨宸ユキ(y猫)绱氾紙-40掳C 鑷� 85掳C锛�

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XC6SLX75-2CSG484C 鎻愪緵浜嗗挤(qi谩ng)澶х殑鍙法绋嬮倧杓兘鍔�锛屾敮鎸佺敤鎴舵牴鎿�(j霉)闇�姹傞潏娲诲畾鍒跺姛鑳�銆傚畠闆嗘垚浜嗚睈瀵岀殑纭欢璩囨簮锛屽寘鎷ぇ閲� CLB锛圕onfigurable Logic Block锛夈�丅lock RAM 鍜� DSP Slice銆�
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銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栬ō(sh猫)鍌欎腑鐨勬暩(sh霉)鎿�(j霉)閲囬泦鑸囨帶鍒剁郴绲�(t菕ng)銆�
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銆�銆�3. 閫氫俊鍩虹珯涓殑淇¤櫉铏曠悊鍠厓銆�
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鏇夸唬鍨嬭櫉

XC6SLX75T-2FGG484C
銆�銆�XC6SLX75-3CSG484C
銆�銆�XC6SLX75T-3FGG484C

xc6slx75-2csg484c鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xc6slx75-2csg484c璩囨枡 鏇村>

  • 鍨嬭櫉
  • 鎻忚堪
  • 鍝佺墝
  • 闁辫涓嬭級

xc6slx75-2csg484c鍙冩暩(sh霉)

  • 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″S6 Family Overview
  • 妯�(bi膩o)婧�(zh菙n)鍖呰84
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪Spartan® 6 LX
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  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)74637
  • RAM 浣嶇附瑷�3170304
  • 杓稿叆/杓稿嚭鏁�(sh霉)328
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲1.14 V ~ 1.26 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害0°C ~ 85°C
  • 灏佽/澶栨484-FBGA锛孋SPBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�484-CSPBGA
  • 鍏跺畠鍚嶇ū122-1776XC6SLX75-2CSG484C-ND