鏅傞枔锛�2025/5/8 10:14:15
闁辫畝锛�29
XC6SLX75-L1CSG484I 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 鐨勪竴鍊嬪叿楂斿瀷铏�銆傝┎鍣ㄤ欢鍩轰簬 40nm 宸ヨ棟鎶�琛撳埗閫狅紝鍏锋湁楂橀泦鎴愬害銆佷綆鍔熻�楀拰闈堟椿鎬у挤鐨勭壒榛�銆係partan-6 绯诲垪涓昏闈㈠悜涓鎳夌敤甯傚牬锛岄仼鐢ㄤ簬闇�瑕侀珮鎬ц兘鍜屾垚鏈劒(y艒u)鍖栫殑鍫存櫙銆俋C6SLX75-L1CSG484I 鎻愪緵浜嗚睈瀵岀殑閭忚集璩囨簮銆佸祵鍏ュ紡濉婂瓨鍎插櫒銆丏SP 鐗囦互鍙婂绋� I/O 鎺ュ彛閰嶇疆銆�
鍨嬭櫉锛歑C6SLX75-L1CSG484I
銆�銆�绯诲垪锛歋partan-6
銆�銆�宸ヨ棟锛�40nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細75,360
銆�銆�鐗囦笂瀛樺劜鍣細239Kb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細160
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細324
銆�銆�灏佽椤炲瀷锛欳SG (Ceramic Super Grid)
銆�銆�寮曡叧鏁�(sh霉)锛�484
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�閰嶇疆妯″紡锛氬緸 Slave Serial (S)銆丼lave Parallel (P)銆丮aster SelectMAP (M)
銆�銆�闆绘簮闆诲锛�1.2V 鏍稿績锛�1.5V 鎴� 3.3V I/O
XC6SLX75-L1CSG484I 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵锛氭敮鎸佹渶楂� 500 MHz 鐨勬檪閻橀牷鐜囥��
銆�銆�2. 鍏х疆 DSP Slice锛氬寘鍚� 160 鍊嬪皥鐢� DSP 鍠厓锛岃兘澶犲姞閫熶箻娉曠疮鍔犻亱绠楃瓑浠诲嫏銆�
銆�銆�3. 澶у閲忓瓨鍎茶硣婧愶細鎻愪緵楂橀仈 239Kb 鐨勫垎甯冨紡鍜屽瀛樺劜鍣ㄨ硣婧�銆�
銆�銆�4. 闈堟椿鐨� I/O 鏀寔锛氬吋瀹瑰绋婧栨帴鍙ｅ崝(xi茅)璀�锛屽 PCIe銆丩VDS 鍜� SPI銆�
銆�銆�5. 鍔熻�楀劒(y艒u)鍖栬ō瑷堬細閲囩敤绱扮矑搴︽檪閻橀杸鎺ф妧琛撳拰鍙伕鐨� PowerDown 妯″紡闄嶄綆鑳借�椼��
銆�銆�6. 澧炲挤鐨勫畨鍏ㄦ�у姛鑳斤細鏀寔浣嶆祦鍔犲瘑鍜岃獚璀変互淇濊鐭ヨ瓨鐢�(ch菐n)娆�銆�
銆�銆�7. 鏄撲簬浣跨敤鐨勯枊鐧�(f膩)宸ュ叿锛氶�氶亷 Xilinx ISE Design Suite 鎻愪緵瀹屾暣鐨勯枊鐧�(f膩)鐠�(hu谩n)澧�銆�
瑭插瀷铏� FPGA 鍙唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 閫氫俊瑷倷锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑淇¤櫉铏曠悊妯″銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬閬嬪嫊鎺у埗銆佹暩(sh霉)鎿�(j霉)閲囬泦鍜屽鏅傜洠(ji膩n)鎺х郴绲�(t菕ng)銆�
銆�銆�3. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細瀵︾従(xi脿n)瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮风瓑鍔熻兘銆�
銆�銆�4. 閱�(y墨)鐧傞浕瀛愶細鏀寔瓒呰伈娉㈡垚鍍忋�佹牳纾佸叡鎸巸鎻忓剙绛夐啱(y墨)鐧傚剙鍣�銆�
銆�銆�5. 娓│鑸囨脯閲忥細妲嬪缓楂樻�ц兘娓│骞宠嚭鎴栦俊铏熷垎鏋愬剙銆�
銆�銆�6. 娑堣不椤為浕瀛愮敘(ch菐n)鍝侊細濡傛暩(sh霉)瀛楅浕瑕�銆佹闋傜洅绛夌敘(ch菐n)鍝佷腑鐨勬牳蹇冩帶鍒跺櫒銆�
XC6SLX75T-CSG484C, XC6SLX75T-CSG484I
