XC7A35T-3CSG325I 鏅�(sh铆)闁擄細2025/5/23 8:25:48 闁辫畝锛�18

XC7A35T-3CSG325I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA 鑺墖锛屽爆浜庨珮鎬ц兘銆佷綆鍔熻€楃殑 28nm 宸ヨ棟鐢�(ch菐n)鍝�銆侫rtix-7 绯诲垪鑺墖寤ｆ硾鎳�(y墨ng)鐢ㄤ簬閫氫俊銆佹秷璨�(f猫i)闆诲瓙銆佸伐妤�(y猫)鎺у埗鍜岄啱(y墨)鐧傝ō(sh猫)鍌欑瓑闋�(l菒ng)鍩�锛屾彁渚涘崜瓒婄殑閭忚集瀵嗗害銆佷俊铏�(h脿o)铏曠悊鑳藉姏鍜岀郴绲�(t菕ng)闆嗘垚搴�銆�
銆€銆€瑭插瀷铏�(h脿o)閲囩敤 CSG325 灏佽锛岄仼鐢ㄤ簬闇€瑕佺穵婀婅ō(sh猫)瑷�(j矛)鍜岄珮 I/O 寮曡叧鏁�(sh霉)閲忕殑鎳�(y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆傚叾 -3 閫熷害绛夌礆(j铆)琛ㄦ槑瀹冨叿鏈夎純楂樼殑鎬ц兘琛ㄧ従(xi脿n)锛岃兘澶犳豢瓒抽珮閫熸暩(sh霉)鎿�(j霉)鍌宠几鍜屽京(f霉)闆滈倧杓亱(y霉n)绠楃殑闇€姹�銆�

鍙冩暩(sh霉)

绯诲垪锛欰rtix-7
銆€銆€鍨嬭櫉(h脿o)锛歑C7A35T-3CSG325I
銆€銆€宸ヨ棟锛�28nm
銆€銆€FPGA 瑕�(gu墨)妯★細35K Logic Cells
銆€銆€RAM锛�1.4Mb Distributed RAM, 2Mb Block RAM
銆€銆€DSP Slice 鏁�(sh霉)閲忥細90
銆€銆€閰嶇疆妯″紡锛歋electMAP銆丮aster/Slave SPI銆丅PI
銆€銆€I/O Bank锛�3.3V, 2.5V, 1.8V, 1.5V, 1.2V
銆€銆€灏佽锛欳SG325
銆€銆€閫熷害绛夌礆(j铆)锛�-3

鐗规€�

XC7A35T-3CSG325I 鎻愪緵璞愬瘜鐨勭壒鎬т互鏀寔澶氭ǎ鍖栫殑鎳�(y墨ng)鐢ㄩ渶姹�銆傞鍏�锛屽叾鍩轰簬 28nm 宸ヨ棟鍒堕€�锛岀⒑淇濅簡浣庡姛鑰楃殑鍚屾檪(sh铆)瀵�(sh铆)鐝�(xi脿n)浜嗛珮瀵嗗害閭忚集鍠厓闆嗘垚銆傚叾娆★紝鑺墖鍏�(n猫i)缃ぇ閲� DSP Slice锛屽彲鏈夋晥鍔犻€熸诞榛�(di菐n)瑷�(j矛)绠�銆佹烤娉㈠櫒鍜屽叾浠栨暩(sh霉)瀛�(xu茅)瀵嗛泦鍨嬩换鍕�(w霉)銆�
銆€銆€姝ゅ锛岃┎鍣ㄤ欢鏀寔澶氱ó瀛樺劜(ch菙)鍣ㄦ帴鍙ｉ(l猫i)鍨嬶紙濡� DDR3 鍜� QDR II+锛�锛屽苟鍏峰倷闈堟椿鐨勬檪(sh铆)閻樼鐞嗗伐鍏凤紙Clock Management Tiles锛�銆傞€氶亷(gu貌)鍏�(n猫i)宓� PCIe 纭牳妯″锛屽彲杓曟澗瀵�(sh铆)鐝�(xi脿n)鑸囦富姗�(j墨)绯荤当(t菕ng)鐨勪簰鑱�(li谩n)銆傚叾 I/O Bank 鏀寔澶氶浕澹撴(bi膩o)婧�(zh菙n)锛屾柟渚块仼閰嶄笉鍚屽瑷�(sh猫)銆�
銆€銆€鍦ㄩ枊(k膩i)鐧�(f膩)鏂归潰锛孹ilinx 鎻愪緵 Vivado Design Suite 闆嗘垚闁�(k膩i)鐧�(f膩)鐠�(hu谩n)澧冿紝骞姪鐢ㄦ埗蹇€熷畬鎴� RTL 绶ㄧ⒓銆佺稖鍚�銆佸竷灞€甯冪窔鍙婇(y脿n)璀夊伐浣溿€傚悓鏅�(sh铆)锛岃姱鐗囧吋瀹圭涓夋柟 IP 鏍歌硣婧愬韩(k霉)锛岄€�(j矛n)涓€姝ョ啊(ji菐n)鍖栦簡寰�(f霉)闆滆ō(sh猫)瑷�(j矛)娴佺▼銆�

鎳�(y墨ng)鐢�

XC7A35T-3CSG325I 甯哥敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆€銆€1. 宓屽叆寮忚瑕�(ju茅)绯荤当(t菕ng)锛氬寘鎷(j墨)鍣ㄨ瑕�(ju茅)銆佸伐妤�(y猫)鐩告(j墨)绛�锛屽緱鐩婁簬鍏跺皪(du矛)鍦栧儚铏曠悊绠楁硶鐨勬敮鎸佽兘鍔涖€�
銆€銆€2. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細渚嬪灏忓瀷鍩虹珯銆佺劇(w煤)绶氭帴鍏ラ粸(di菐n)浠ュ強鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗗钩鑷�(t谩i)銆�
銆€銆€3. 娓�(c猫)瑭﹁垏娓�(c猫)閲忚ō(sh猫)鍌欙細鍒╃敤 FPGA 瀵�(sh铆)鐝�(xi脿n)瀵�(sh铆)鏅�(sh铆)淇¤櫉(h脿o)閲囬泦銆佸垎鏋愬拰鐢熸垚鍔熻兘銆�
銆€銆€4. 閱�(y墨)鐧傚剙鍣細濡傝秴鑱茶ê鏂峰剙涓殑娉㈡潫褰㈡垚鍣ㄩ儴鍒嗭紝渚濋潬鍏堕珮搴﹀苟琛屽寲鏋舵(g貌u)鍎�(y艒u)鍕�(sh矛)銆�
銆€銆€5. 娑堣不(f猫i)椤�(l猫i)闆诲瓙鐢�(ch菐n)鍝侊細娓告埐姗�(j墨)鍦栧舰鍔犻€熷崱鎴栧叾浠栧濯掗珨铏曠悊鐩搁棞(gu膩n)纭欢涓櫦(f膩)鎻噸瑕佷綔鐢�銆�