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闁辫畝锛�35
XC7K410T-3FB900E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Kintex-7 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏熴�傝┎绯诲垪鑺墖涓昏鐢ㄤ簬楂樻�ц兘瑷堢畻銆侀�氫俊绯荤当(t菕ng)銆佽闋诲拰鍦栧儚铏曠悊绛夐牁鍩�銆侹intex-7 绯诲垪绲愬悎浜嗛珮閭忚集瀵嗗害銆侀珮閫熶覆琛岄�ｆ帴鑳藉姏浠ュ強寮峰ぇ鐨� DSP 鍔熻兘锛岄仼鐢ㄤ簬闇�瑕侀珮甯跺鍜屼綆寤堕伈鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�XC7K410T-3FB900E 鐗瑰垾閬╁悎浜庝腑绔噳鐢ㄩ渶姹傦紝鍏惰睈瀵岀殑 I/O 璩囨簮鍜屽彲閰嶇疆閭忚集濉婁娇鍏舵垚鐐鸿ū澶氬京闆滄暩(sh霉)瀛楃郴绲�(t菕ng)鐨勭悊鎯抽伕鎿�銆�
鍨嬭櫉锛歑C7K410T-3FB900E
銆�銆�绯诲垪锛欿intex-7
銆�銆�鍝佺墝锛歑ilinx
銆�銆�灏佽椤炲瀷锛欶BGA900
銆�銆�閰嶇疆閭忚集鍠厓锛圕LB锛夛細262,800
銆�銆�鏌ユ壘琛紙LUT锛夛細414,720
銆�銆�瑙哥櫦(f膩)鍣細829,440
銆�銆�DSP Slice锛�550
銆�銆�RAM Block锛�18 Kb锛夛細1,140
銆�銆�鐢ㄦ埗 I/O 鏁�(sh霉)閲忥細444
銆�銆�鏈�澶у伐浣滈牷鐜囷細绱� 624 MHz
銆�銆�渚涢浕闆诲锛�1.0V 鏍稿績闆诲锛�1.8V 鎴� 3.3V I/O 闆诲
銆�銆�婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�宸ヨ棟绡�(ji茅)榛烇細28nm
XC7K410T-3FB900E 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵锛氬熀浜� 28nm 宸ヨ棟鍒堕�狅紝鎻愪緵浜嗗崜瓒婄殑鎬ц兘鍔熻�楁瘮锛岃兘澶犳敮鎸侀珮閬� 624MHz 鐨勬檪閻橀牷鐜�銆�
銆�銆�2. 寮峰ぇ鐨� DSP 鍔熻兘锛氶泦鎴愪簡 550 鍊� DSP Slice锛屾瘡鍊� Slice 鍖呭惈 27x18 涔樻硶鍣ㄥ拰 48 浣嶅姞娉曞櫒/绱姞鍣紝闈炲父閬╁悎閫茶寰╅洔鐨勬暩(sh霉)瀛搁亱绠�銆�
銆�銆�3. 璞愬瘜鐨勫瓨鍎茶硣婧愶細鎿佹湁 1,140 鍊� 18kb 鐨� RAM Block锛屽彲浠ラ潏娲诲湴閰嶇疆鐐哄垎甯冨紡 RAM 鎴栧鐙� RAM锛屾豢瓒冲悇绋暩(sh霉)鎿�(j霉)绶╁瓨闇�姹傘��
銆�銆�4. 澶ч噺鐨� I/O 鏀寔锛氭彁渚涘閬� 444 鍊嬬敤鎴跺彲鐢ㄧ殑 I/O锛屾敮鎸佸绋婧栨帴鍙ｅ崝(xi茅)璀帮紝濡� PCIe銆丏DR3 鍜屽崈鍏嗕互澶恫(w菐ng)绛�銆�
銆�銆�5. 鍏х疆纭牳妯″锛氬寘鍚� PCIe Gen2 x8 妯″鍜� 16 鍊嬮泦鎴愬紡 GTX 鏀剁櫦(f膩)鍣�锛屾敮鎸侀珮閬� 6.6Gbps 鐨勫偝杓搁�熺巼銆�
銆�銆�6. 楂樺彲闈犳�цō瑷堬細鏀寔閮ㄥ垎鍕曟厠(t脿i)閲嶆鍔熻兘锛圥R锛�锛屽厑瑷卞湪閬嬭鏅傞噸鏂伴厤缃壒瀹氬崁(q奴)鍩熻�岀劇闇�閲嶅暉鏁村�嬬郴绲�(t菕ng)銆�
銆�銆�7. 鏄撶敤鎬у伐鍏烽張锛氶厤濂楁湁 Vivado Design Suite 瑷▓宸ュ叿锛岀啊鍖栦簡闁嬬櫦(f膩)娴佺▼骞舵彁楂樹簡鏁堢巼銆�
XC7K410T-3FB900E 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氱敤浜庡熀绔欐敹鐧�(f膩)淇℃銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑淇¤櫉铏曠悊銆�
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細閬╃敤浜庤闋荤法纰�/瑙ｇ⒓銆佸湒鍍忓寮峰強瑷堢畻姗熻瑕轰换鍕欍��
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銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬閬嬪嫊鎺у埗銆佹鍣ㄤ汉鎶�琛撲互鍙婂鏅傜洠(ji膩n)鎺х郴绲�(t菕ng)銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細鏀寔瓒呰伈娉㈣ō鍌�銆丆T 鎺冩弿鍎�鍙婂叾浠栭啱(y墨)鐧傚奖鍍忕郴绲�(t菕ng)鐨勫湒鍍忚檿鐞�銆�
銆�銆�6. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細瀵︾従(xi脿n)鍔犲瘑瑙ｅ瘑銆佹暩(sh霉)鎿�(j霉)澹撶府绛夊姛鑳�锛屾彁鍗囨湇鍕欏櫒鎬ц兘銆�
XC7K410T-2FBG676C
銆�銆�XC7K410T-2FFG676I
銆�銆�XC7K410T-3FBG676C
