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鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�	XC7K410T-3FFG676E
鎻忚堪	闆嗘垚闆昏矾FPGA 400 I / O 676FCBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	Xilinx鍏徃
绯诲垪	Kintex?-7
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	0.97V?1.03V
宸ヤ綔婧害	0掳C?100掳C(TJ)
鍖呰/绠�	676-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	676-FCBGA(27x27)
鍩烘湰闆朵欢铏�	XC7K410T

鐢�(ch菐n)鍝佸湒鐗�

XC7K410T-3FFG676E

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍒堕€犲晢鍖呰瑾槑	FBGA-676
绗﹀悎REACH	鏄�
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	娲绘€�
鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
鏈€澶ф檪(sh铆)閻橀牷鐜�	1412.0 MHz
CLB-Max鐨勭祫鍚堝欢閬�	0.58绱嶇
JESD-30浠ｇ⒓	S-PBGA-B676
JESD-609浠ｇ⒓	e1
绺絉AM浣�	29306880
CLB鏁�(sh霉)閲�	31775.0
杓稿叆鏁�(sh霉)閲�	400.0
閭忚集鍠厓鏁�(sh霉)	406720.0
杓稿嚭鏁�(sh霉)閲�	400.0
绔瓙鏁�(sh霉)	676
绲勭箶	31775 CLBS
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA676,26X26,40
鍖呰褰㈢媭	鍥涙柟褰�
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
闆绘簮	1,1.8,3.3
搴ч珮	3.37姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.0浼�
鏈€灏忎緵闆婚浕澹�	0.97浼�
鏈€澶ч浕婧愰浕澹�	1.03浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閵€/閵�(Sn96.5Ag3.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
闀峰害	27.0姣背
瀵害	27.0姣背

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

RoHS鐙€鎱�(t脿i)	绗﹀悎ROHS3
姘村垎鏁忔劅鎬ф按骞�(MSL)	4(72灏忔檪(sh铆))

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鐢ㄤ簬PCIExpress?(PCIe)鐨勯泦鎴愭ā濉�锛屾渶澶氬彲鐢ㄤ簬x8 Gen3绔粸(di菐n)鍜屾牴绔彛瑷�(sh猫)瑷�(j矛)銆�
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