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XC7S25-1CSGA225C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛変腑鐨勪竴鍊嬪瀷铏�銆侫rtix-7 绯诲垪 FPGA 闈㈠悜浣庡姛鑰楀拰楂樻�ц兘鐨勬噳鐢ㄩ渶姹�锛岄仼鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆侀啱(y墨)鐧傝ō鍌�銆佽埅绌鸿埅澶╃瓑闋�(l菒ng)鍩�銆�
銆�銆�瑭插瀷铏熺殑 XC7S25 灞簬灏忓瀷鍖� FPGA锛屽叿鏈夎純浣庣殑閭忚集璩囨簮鍜岃純灏戠殑 DSP 鍒囩墖锛岄仼鍚堜腑浣庣鎳夌敤鍫村悎銆傚叾灏佽褰㈠紡鐐� CSGA225锛岃〃绀虹穵婀婂瀷鐞冩煹闄ｅ垪灏佽锛屽紩鑵虫暩(sh霉)鐐� 225銆�
鍣ㄤ欢绯诲垪锛欰rtix-7
銆�銆�FPGA 鍨嬭櫉锛歑C7S25
銆�銆�閫熷害绛夌礆锛�-1
銆�銆�灏佽椤炲瀷锛欳SGA225
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細24,480
銆�銆�DSP 鍒囩墖鏁�(sh霉)閲忥細60
銆�銆�BRAM 鏁�(sh霉)閲忥細50KB
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�174
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�宸ヨ棟绡�(ji茅)榛烇細28nm
銆�銆�鍔熻�楄寖鍦嶏細鍏稿瀷鍊肩磩 1W
XC7S25-1CSGA225C 鎻愪緵浜嗚睈瀵岀殑纭欢璩囨簮鍜岄潏娲荤殑鏋舵(g貌u)瑷▓銆�
銆�銆�1. 閲囩敤 UltraScale 鏋舵(g貌u)锛屾敮鎸侀珮鍚炲悙閲忕殑鏁�(sh霉)鎿�(j霉)铏曠悊浠诲嫏銆�
銆�銆�2. 鍏�(n猫i)缃� Block RAM 鍜屽垎甯冨紡 RAM 璩囨簮锛屽彲鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╁瓨鎴�?q奴)宕縁(xi脿n)鏈夐檺鐙�鎱�(t脿i)姗�銆�
銆�銆�3. DSP48E1 鐗囦笂妯″鎻愪緵楂樻晥鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗚兘鍔涳紝濡傛烤娉㈠櫒瑷▓銆丗FT 瀵︾従(xi脿n)绛�銆�
銆�銆�4. 鏀寔澶氱ó涓茶鎺ュ彛妯欐簴锛屼緥濡� Gigabit Transceivers锛屽偝杓搁�熺巼鍙仈 6.6Gbps銆�
銆�銆�5. 鎻愪緵闈堟椿鐨勬檪閻樼鐞嗗伐鍏凤紙Clock Management Tile锛�锛屽寘鎷� PLL 鍜� MMCM 妯″锛岀敤浜庣敓鎴愮簿纰虹殑鏅傞悩淇¤櫉銆�
銆�銆�6. 鍙�氶亷 SPI銆丅PI 鎴栧叾浠栨ā寮忛�茶澶栭儴閰嶇疆瀛樺劜鍣ㄥ姞杓�锛岀啊鍖栭枊鐧�(f膩)娴佺▼銆�
銆�銆�7. 鍔熻�楀劒(y艒u)鍖栨妧琛�(sh霉)浣胯姱鐗囪兘澶犲湪淇濊瓑鎬ц兘鐨勫悓鏅傞檷浣庤兘鑰�锛岀壒鍒ラ仼鍚堜究鏀滃紡鎴栭浕姹犱緵闆昏ō鍌�銆�
銆�銆�8. 鎻愪緵 Vivado 瑷▓濂椾欢鏀寔锛屾柟渚跨敤鎴跺畬鎴愬緸瑷▓杓稿叆鍒扮稖鍚堛�佸竷灞�甯冪窔銆佷豢鐪熼璀夌殑鍏ㄦ祦绋嬫搷浣�銆�
鐢变簬鍏跺劒(y艒u)鐣扮殑鎬ц兘鑸囧姛鑰楀钩琛�锛孹C7S25-1CSGA225C 寤ｆ硾鎳夌敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栨帶鍒讹細瀵︽檪鏁�(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞�锛岄亱鍕曟帶鍒剁畻娉曞鐝�(xi脿n)銆�
銆�銆�2. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛氬湒鍍忛爯铏曠悊銆佺壒寰佹彁鍙栧強妯″紡璀樺垾绛夊姛鑳姐��
銆�銆�3. 閫氫俊鍩虹(ch菙)瑷柦锛氬皬鍨嬪熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鍗�(xi茅)璀拌В鏋愯垏杞�(zhu菐n)鐧�(f膩)銆�
銆�銆�4. 閱�(y墨)鐧傞浕瀛愯ō鍌欙細瓒呰伈娉㈡垚鍍忓墠绔俊铏熼張璺ō瑷�锛屽績闆诲湒鐩�(ji膩n)娓剙鍣ㄧ殑鏍稿績铏曠悊鍠厓銆�
銆�銆�5. 娑堣不椤為浕瀛愮敘(ch菐n)鍝侊細鍦栧舰鍔犻��銆侀煶闋荤法瑙ｇ⒓浠ュ強瑕栭牷娴佸獟楂旀挱鏀惧劒(y艒u)鍖�銆�
銆�銆�6. 鏁欒偛绉戠爺骞宠嚭锛氫綔鐐哄ぇ瀛歌绋嬪椹楁澘鐨勬牳蹇冨櫒浠�锛屽公鍔╁鐢熷缈� FPGA 闁嬬櫦(f膩)鎶�鑳姐��
XC7S25-2CSGA225C
銆�銆�XC7S25-3CSGA225C
