鏅傞枔锛�2025/4/29 16:26:59
闁辫畝锛�33
XC7V585T-1FFG1761I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪 FPGA 鑺墖涔嬩竴銆傝┎绯诲垪鑺墖閲囩敤 28nm 鍒剁▼宸ヨ棟鍒堕��锛屽叿鏈夐珮鎬ц兘銆侀珮瀵嗗害閭忚集璩囨簮浠ュ強璞愬瘜鐨勬帴鍙ｅ姛鑳�銆俋C7V585T 闆嗘垚浜� 580K 閭忚集鍠厓锛屾敮鎸侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄥ拰澶у閲忕殑宓屽叆寮忓瓨鍎插櫒锛岄仼鐢ㄤ簬寰╅洔鐨勮ō瑷堝牬鏅閫氫俊銆佸湒鍍忚檿鐞嗐�佽埅绌鸿埅澶╃瓑闋樺煙銆�
銆�銆�Virtex-7 绯诲垪閫氶亷闆嗘垚澶ч噺 DSP Slice 鍜� Block RAM锛岃兘澶犳豢瓒冲绋▓绠楀瘑闆嗗瀷浠诲嫏鐨勯渶姹�銆傛澶�锛屽叾鍏�(n猫i)缃殑 PCIe 纭牳鍙姞閫熻垏涓绘鎴栧叾浠栬ō鍌欑殑鏁�(sh霉)鎿�(j霉)浜や簰銆�
鍨嬭櫉锛歑C7V585T-1FFG1761I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex-7
銆�銆�灏佽椤炲瀷锛欶FG1761
銆�銆�I/O 鏁�(sh霉)閲忥細1048
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master Parallel
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細580K
銆�銆�Block RAM 瀹归噺锛�36.9Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2320
銆�銆�涓茶鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲忥細24
銆�銆�鏈�澶т覆琛屾敹鐧�(f膩)鍣ㄩ�熺巼锛�6.5Gbps
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銆�銆�瑭茶姱鐗囬倓闆嗘垚浜嗚睈瀵岀殑澶栬ō閬搁爡锛屽寘鎷� PCIe Gen3 纭牳銆佸崈鍏嗕互澶恫(w菐ng) MAC銆乁SB 鎺у埗鍣ㄧ瓑妯″锛屼究浜庡鐝�(xi脿n)寰╅洔鐨勭郴绲�(t菕ng)绱氳В姹烘柟妗堛��
銆�銆�Xilinx 鎻愪緵浜嗛厤濂楃殑 Vivado 瑷▓宸ュ叿閺�锛岀敤浜� XC7V585T 鐨勯枊鐧�(f膩)宸ヤ綔锛屽緸 RTL 绶ㄥ鍒扮稖鍚�銆佸竷灞�甯冪窔鍧囪兘楂樻晥瀹屾垚銆傛澶�锛岃┎绯诲垪鑺墖鏀寔閮ㄥ垎鍕曟厠(t脿i)閲嶆(g貌u)鎶�琛�锛屽厑瑷卞湪閬嬭鏅傚皪鐗瑰畾鍗�(q奴)鍩熼�茶閲嶆柊閰嶇疆锛屽緸鑰屽劒(y艒u)鍖栧姛鑰楀拰鎬ц兘琛ㄧ従(xi脿n)銆�
XC7V585T 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鎬ц兘瑷堢畻鍜屽京闆滀俊铏熻檿鐞嗙殑闋樺煙锛�
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬彲鐢ㄤ簬鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙绛夎ō鍌欎腑鐨勬暩(sh霉)鎿�(j霉)鍖呰檿鐞嗗拰鍗�(xi茅)璀拌綁(zhu菐n)鎻�銆�
銆�銆�2. 瑕栭牷鍜屽湒鍍忚檿鐞嗭細瀵︾従(xi脿n)瀵︽檪瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮风瓑鍔熻兘銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細鎻愪緵蹇�熼熆鎳夋帶鍒跺洖璺強鍒嗗竷寮忔帶鍒剁郴绲�(t菕ng)鐨勬牳蹇冭檿鐞嗗櫒銆�
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銆�銆�6. 鑸┖鑸ぉ锛氫綔鐐鸿(w猫i)鏄熻級鑽锋垨椋涜鍣ㄦ帶鍒跺柈鍏冧腑鐨勬牳蹇冭▓绠楅儴浠躲��
XC7V585T-2FFG1761I
銆�銆�XC7V585T-3FFG1761I
