鏅傞枔锛�2025/5/8 19:39:20
闁辫畝锛�33
XCKU15P-2FFVA1760E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale 绯诲垪楂樼 FPGA 鑺墖锛屽熀浜� 20nm 宸ヨ棟鍒堕��銆傝┎鍨嬭櫉涓昏闈㈠悜楂樻�ц兘瑷堢畻銆侀�氫俊绯荤当(t菕ng)銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熶互鍙婅埅绌鸿埅澶╃瓑闋樺煙鐨勬噳鐢ㄩ渶姹�銆�
銆�銆�姝よ姱鐗囨彁渚涘ぇ瑕�(gu墨)妯￠倧杓硣婧愬拰璞愬瘜鐨� IO 鎺ュ彛閰嶇疆锛屾敮鎸佸绋珮閫熶覆琛屽崝(xi茅)璀�锛屽苟涓斿叿鍌欏挤澶х殑鍙法绋嬭兘鍔�锛屼娇鍏惰兘澶犻潏娲婚仼閰嶅京闆滅殑瑷▓鍫存櫙銆�
鍨嬭櫉锛歑CKU15P-2FFVA1760E
銆�銆�宸ヨ棟鍒剁▼锛�20nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 195K
銆�銆�RAM 瀹归噺锛�34.6Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細4800
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� Master SPI
銆�銆�I/O Bank 鏁�(sh霉)閲忥細52
銆�銆�鏈�澶х敤鎴� I/O 寮曡叧鏁�(sh霉)锛�920
銆�銆�灏佽椤炲瀷锛欶FVA1760
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�渚涢浕闆诲锛�1.0V 鏍稿績闆诲锛岃紨鍔╅浕澹撶偤 1.8V/3.3V
XCKU15P-2FFVA1760E 灞簬 Xilinx Kintex UltraScale 绯诲垪锛屽叿鏈変互涓嬮’钁楃壒鎬э細
銆�銆�1. 楂樻�ц兘鏋舵(g貌u)锛氶噰鐢� UltraScale 鏋舵(g貌u)锛屽劒(y艒u)鍖栦簡鏅傞悩绠＄悊銆佷俊铏熷偝杓歌矾寰戝欢閬插拰鍚炲悙閲�銆�
銆�銆�2. 澶ц(gu墨)妯￠倧杓硣婧愶細鍖呭惈瓒呴亷 195K 鐨勯倧杓柈鍏冿紝閬╁悎铏曠悊寰╅洔鐨勭畻娉曞拰鏁�(sh霉)鎿�(j霉)娴�銆�
銆�銆�3. 鍏�(n猫i)缃� DSP 妯″锛氬閬� 4800 鍊� DSP Slice锛岄仼鐢ㄤ簬娴粸閬嬬畻鍜屾暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�4. 楂橀�熸敹鐧�(f膩)鍣細闆嗘垚澶氬�嬮珮閬� 15.75Gbps 鐨� GTH 鏀剁櫦(f膩)鍣�锛屾豢瓒抽珮閫熼�氫俊鎺ュ彛鐨勯渶姹�銆�
銆�銆�5. 鍙摯灞曞瓨鍎插櫒鎺ュ彛锛氭敮鎸� DDR4銆丏DR3銆丷LDRAM3 鍜� QDR-IV 绛夊瓨鍎插櫒椤炲瀷锛屾彁渚涢珮鏁堢殑鍏�(n猫i)瀛樿í鍟忚兘鍔�銆�
銆�銆�6. 澧炲挤鐨勮(di脿o)瑭﹀姛鑳斤細鍏�(n猫i)缃� Vivado 瑷▓濂椾欢鏀寔锛屾彁渚涘叏闈㈢殑闁嬬櫦(f膩)鍜岃(di脿o)瑭﹀伐鍏烽泦銆�
銆�銆�7. 浣庡姛鑰楄ō瑷堬細閫氶亷鍕曟厠(t脿i)鍔熻�楄(di脿o)绡�(ji茅)鎶�琛撳拰鍒嗗崁(q奴)闆绘簮绠＄悊闄嶄綆鏁撮珨鑳借��銆�
XCKU15P-2FFVA1760E 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗚垏鍗�(xi茅)璀拌綁(zhu菐n)鎻�銆�
銆�銆�2. 楂樻�ц兘瑷堢畻锛氱敤浜庡姞閫熺瀛歌▓绠�銆侀噾铻嶅缓妯″拰姗熷櫒瀛哥繏瑷撶反銆�
銆�銆�3. 瑕栭牷寤ｆ挱锛氬鐝�(xi脿n)瀵︽檪瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮峰拰鏍煎紡杞�(zhu菐n)鎻�銆�
銆�銆�4. 閱�(y墨)鐧傛垚鍍忚ō鍌欙細鏀寔楂樺垎杈ㄧ巼褰卞儚铏曠悊鍜屽鏅傚垎鏋愩��
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃诧細閬╂噳鍤磋嫑鐠�(hu谩n)澧冧笅鐨勪俊铏熻檿鐞嗗拰鎺у埗浠诲嫏銆�
銆�銆�6. 鏁�(sh霉)鎿�(j霉)涓績锛氭彁渚涚恫(w菐ng)绲″姞閫�銆佹暩(sh霉)鎿�(j霉)澹撶府鍜屽姞瀵嗙瓑鍔熻兘銆�
銆�銆�7. 宸ユキ(y猫)鑷嫊鍖栵細瀵︾従(xi脿n)寰╅洔鐨勯亱鍕曟帶鍒跺拰姗熷櫒浜鸿瑕虹郴绲�(t菕ng)銆�
XCKU15P-1FFVA1760E
銆�銆�XCKU15P-3FFVA1760E
