XCVU125-1FLVA2104I 鏅�(sh铆)闁擄細2025/6/4 17:08:28 闁辫畝锛�11

XCVU125-1FLVA2104I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖涓殑涓€鍊�(g猫)鍨嬭櫉(h脿o)銆傝┎绯诲垪鑺墖閲囩敤鍏堥€�(j矛n)鐨� FinFET 宸ヨ棟鎶€琛�(sh霉)鍒堕€狅紝鍏峰倷楂樺瘑搴﹂倧杓柈鍏�銆侀珮閫熸敹鐧�(f膩)鍣ㄥ拰璞愬瘜鐨� DSP 妯″璩囨簮銆俋CVU125 鐗瑰垾閬╁悎鐢ㄤ簬楂樻€ц兘瑷�(j矛)绠椼€佺恫(w菐ng)绲�(lu貌)閫氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻€熶互鍙婂湒鍍忚檿鐞嗙瓑闋�(l菒ng)鍩�銆�
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鍙冩暩(sh霉)

鍨嬭櫉(h脿o)锛歑CVU125-1FLVA2104I
銆€銆€鍝佺墝锛歑ilinx
銆€銆€绯诲垪锛歎ltraScale+
銆€銆€宸ヨ棟鍒剁▼锛�16nm
銆€銆€閰嶇疆妯″紡锛歁ultiBoot
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 125K
銆€銆€DSP Slice 鏁�(sh霉)閲忥細6800
銆€銆€Block RAM 鏁�(sh霉)閲忥細2960
銆€銆€鐢ㄦ埗 I/O 鏁�(sh霉)閲忥細鏈€澶ф敮鎸� 1392
銆€銆€鏀剁櫦(f膩)鍣ㄩ€熺巼锛氶珮閬�(d谩) 32.75 Gbps
銆€銆€灏佽椤炲瀷锛欶LGA (Flip Chip Land Grid Array)
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€渚涢浕闆诲锛氭牳蹇冮浕澹撶偤 0.85V

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XCVU125-1FLVA2104I 鐨勪富瑕佺壒鎬у寘鎷細
銆€銆€1. 楂樻€ц兘鏋舵(g貌u)锛氬熀浜� UltraScale+ 鏋舵(g貌u)锛屾敮鎸侀珮鏁堢殑鏅�(sh铆)搴忔敹鏂傚拰浣庡欢閬茬殑鏁�(sh霉)鎿�(j霉)璺緫銆�
銆€銆€2. 澶у閲忓瓨鍎�(ch菙)璩囨簮锛氬寘鍚鍊�(g猫) Block RAM 鍜屽垎甯冨紡 RAM锛岃兘澶�?q奴)宕縁(xi脿n)寰�(f霉)闆滅殑瀛樺劜(ch菙)鍜屾暩(sh霉)鎿�(j霉)绶╂矕鍔熻兘銆�
銆€銆€3. 寮�(qi谩ng)澶х殑 DSP 鍔熻兘锛氬収(n猫i)缃ぇ閲� DSP Slice锛岄仼鐢ㄤ簬娴粸(di菐n)閬�(y霉n)绠�銆佹烤娉㈠櫒鍜屽叾浠栨暩(sh霉)瀛�(xu茅)瀵嗛泦鍨嬬畻娉曘€�
銆€銆€4. 鏀寔澶氶€熺巼鏀剁櫦(f膩)鍣細鍏锋湁楂橀€熶覆琛屾敹鐧�(f膩)鍣ㄦā濉�锛屽彲閬╂噳(y墨ng)寰炲咕 Gbps 鍒拌秴閬� 30Gbps 鐨勫绋€熺巼銆�
銆€銆€5. 鍙摯(ku貌)灞曟€э細鏀寔澶氱ó澶栬ō(sh猫)鎺ュ彛鍗�(xi茅)璀�锛屼緥濡� PCIe銆丏DR4 鍏�(n猫i)瀛樻帶鍒跺櫒绛夈€�
銆€銆€6. 楂樺彲闈犳€э細閫氶亷纭欢绱�(j铆)绯鹃尟(cu貌)纰硷紙ECC锛変繚璀�(h霉)闂�(gu膩n)閸垫暩(sh霉)鎿�(j霉)锛岀⒑淇濈郴绲�(t菕ng)閬�(y霉n)琛岀┅(w臎n)瀹氭€�銆�
銆€銆€7. 浣庡姛鑰楄ō(sh猫)瑷�(j矛)锛氱祼(ji茅)鍚堝嫊(d貌ng)鎱�(t脿i)闆绘簮绠＄悊鎶€琛�(sh霉)鍜岄潏娲荤殑闆诲瑾�(di脿o)绡€(ji茅)鏂规锛屾湁鏁堥檷浣庢暣楂斿姛鑰楁按骞�銆�

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XCVU125-1FLVA2104I 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浜庢湇鍕�(w霉)鍣ㄥ姞閫熷崱銆丄I 鎺ㄧ悊寮曟搸浠ュ強澶ф暩(sh霉)鎿�(j霉)铏曠悊骞宠嚭(t谩i)銆�
銆€銆€2. 閫氫俊瑷�(sh猫)鍌欙細鏀寔涓嬩竴浠ｇ劇绶氬熀绀�(ch菙)瑷�(sh猫)鏂藉缓瑷�(sh猫)锛屽 5G 鍩虹珯鍜岃矾鐢卞櫒銆�
銆€銆€3. 瑕栭牷寤ｆ挱锛氬(sh铆)鐝�(xi脿n)瀵�(sh铆)鏅�(sh铆)瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮�(qi谩ng)绛夊姛鑳�銆�
銆€銆€4. 閱�(y墨)鐧傛垚鍍忥細鐢ㄤ簬瓒呰伈娉㈣ō(sh猫)鍌�銆丆T 鎺冩弿鍎€绛夐珮绔啱(y墨)鐧傚剙鍣�銆�
銆€銆€5. 宸ユキ(y猫)鑷嫊(d貌ng)鍖栵細鎻愪緵绮剧⒑鎺у埗鑸囬珮鏁堟暩(sh霉)鎿�(j霉)閲囬泦鑳藉姏锛屽姪鍔涙櫤鑳藉埗閫犵櫦(f膩)灞�銆�
銆€銆€6. 鑸┖鑸ぉ锛氭豢瓒宠嫑鍒荤挵(hu谩n)澧冧笅鐨勪换鍕�(w霉)瑕佹眰锛屼繚璀夐暦鏅�(sh铆)闁撶┅(w臎n)瀹氬伐浣�銆�