鏅傞枔锛�2025/4/29 15:36:31
闁辫畝锛�28
XCVU125-1FLVB1760C 鏄竴娆剧敱 Xilinx 鍏徃鐢熺敘鐨勯珮绔� FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗�锛屽爆浜� Virtex UltraScale 绯诲垪銆傝┎绯诲垪 FPGA 閲濆皪楂樻�ц兘瑷堢畻銆佺恫(w菐ng)绲￠�氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熶互鍙婇珮绱氫俊铏熻檿鐞嗙瓑鎳夌敤閫茶浜嗗劒(y艒u)鍖�銆�
銆�銆�姝ゅ瀷铏熺殑 FPGA 鎻愪緵浜嗗ぇ瀹归噺閭忚集璩囨簮銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄣ�佽睈瀵岀殑瀛樺劜鍣ㄦā濉婁互鍙婇潏娲荤殑 I/O 閰嶇疆锛岄仼鐢ㄤ簬闇�瑕侀珮甯跺鍜屽京闆滈倧杓亱绠楃殑鎳夌敤鍫存櫙銆�
鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�绯诲垪锛歏irtex UltraScale
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 125K
銆�銆�瀛樺劜鍣細16MB BRAM锛�32MB ULRAM
銆�銆�DSP Slice 鏁�(sh霉)閲忥細~6800
銆�銆�閰嶇疆妯″紡锛歋electMAP, Master SPI, Slave SPI
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 1728 鍊嬬敤鎴� I/O
銆�銆�渚涢浕闆诲锛�1.0V 鏍稿績闆诲锛�1.8V 杓斿姪闆诲
銆�銆�灏佽椤炲瀷锛欶LVB1760C
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCVU125-1FLVB1760C 鎿佹湁浠ヤ笅闂滈嵉鐗规�э細
銆�銆�1. 楂樻�ц兘鏋舵锛氬熀浜� 20nm 鍒剁▼宸ヨ棟瑷▓锛屾彁渚涘挤澶х殑閭忚集铏曠悊鑳藉姏鍜岄珮鏁堢殑鍔熻�楃鐞�銆�
銆�銆�2. 澶ц(gu墨)妯￠泦鎴愶細鏀寔澶氶仈 125K 鐨勯倧杓柈鍏冿紝鑳藉瀵︾従(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�3. 瓒呴珮閫熶覆琛岄�ｆ帴锛氶泦鎴愪簡楂橀仈 28Gbps 鐨勫閫氶亾 GTH 鏀剁櫦(f膩)鍣紝閬╁悎鐢ㄤ簬楂樺付瀵暩(sh霉)鎿�(j霉)鍌宠几銆�
銆�銆�4. 鍏у祵瀛樺劜鍣細鍖呭惈澶у閲忕殑 Block RAM 鍜� UltraRAM 妯″锛屼究浜庡鐝�(xi脿n)娣卞害绶╂矕鍗�(q奴)鎴栫珐瀛樺姛鑳�銆�
銆�銆�5. DSP 寮曟搸锛氬収缃皥鐢ㄧ殑 DSP48E2 鍠厓锛屽彲楂樻晥瀹屾垚娴粸鏁�(sh霉)鍜屽畾榛炴暩(sh霉)閬嬬畻浠诲嫏銆�
銆�銆�6. 鍙摯灞曟�э細鏀寔澶氱ó澶栬ō鎺ュ彛鍗�(xi茅)璀帮紙濡� PCIe Gen3銆佷互澶恫(w菐ng) MAC锛�锛屾柟渚胯垏澶栭儴绯荤当(t菕ng)灏嶆帴銆�
銆�銆�7. 鍕曟厠(t脿i)閲嶉厤缃細鍏佽ū閮ㄥ垎鍗�(q奴)鍩熷嫊鎱�(t脿i)鏇存柊锛屾彁楂樿硣婧愬埄鐢ㄧ巼骞舵笡灏戝仠姗熸檪闁撱��
瑭茶姱鐗囧唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 楂樻�ц兘瑷堢畻锛氫緥濡傜瀛镐豢鐪�銆侀噾铻嶅垎鏋愮瓑銆�
銆�銆�2. 缍�(w菐ng)绲￠�氫俊锛氬寘鎷矾鐢卞櫒銆佷氦鎻�
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鐢ㄤ綔鏈嶅嫏鍣ㄤ腑鐨勫崝(xi茅)铏曠悊鍣�锛屾彁鍗囩壒瀹氫换鍕欑殑鍩�(zh铆)琛屾晥鐜�銆�
銆�銆�4. 瑕栭牷铏曠悊锛氬鏅傚湒鍍忕法纰艰В纰�銆佽闋绘祦鍌宠几?sh霉)鍙�?br>銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栵細閬嬪嫊鎺у埗銆佹鍣ㄤ汉瑕栬绛�銆�
銆�銆�6. 閱�(y墨)鐧傝ō鍌欙細瓒呰伈娉㈡垚鍍�銆佹牳纾佸叡鎸巸鎻忓剙绛夐啱(y墨)鐧傚剙鍣ㄧ殑鏁�(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞嗐��
銆�銆�7. 鍦嬮槻鑸ぉ锛氶浄閬斾俊铏熻檿鐞�銆佽(w猫i)鏄熼�氫俊绛夌壒娈婄敤閫�銆�
XCVU13P-1FHGB2104E
銆�銆�XCVU9P-2FFVA2104E
銆�銆�XCVU11P-2FLGA2104E
