XCVU125-2FLVA2104I 鏅傞枔锛�2025/5/23 13:00:12 闁辫畝锛�18

XCVU125-2FLVA2104I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex UltraScale 绯诲垪 FPGA 鑺墖锛屽爆浜庨珮绔� FPGA 鐢�(ch菐n)鍝佺窔銆傝┎绯诲垪鑺墖灏堢偤楂樻€ц兘瑷堢畻銆佺恫(w菐ng)绲�(lu貌)铏曠悊鍜屾暩(sh霉)鎿�(j霉)涓績鎳�(y墨ng)鐢ㄨ€岃ō(sh猫)瑷�銆俋CVU125 鎻愪緵浜嗗挤澶х殑閭忚集璩囨簮銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄥ拰璞愬瘜鐨勫瓨鍎插櫒閬搁爡锛岃兘澶犳豢瓒冲京闆滅郴绲�(t菕ng)鐨勯渶姹�銆�
銆€銆€姝ゅ瀷铏熺殑 FPGA 闆嗘垚浜嗗ぇ閲忕殑 DSP 妯″鍜屽祵鍏ュ紡瀛樺劜鍣ㄥ锛岄仼鍚堢敤浜庨渶瑕侀珮鍚炲悙閲忓拰浣庡欢閬茬殑鎳�(y墨ng)鐢ㄥ牬鏅�锛屼緥濡傞珮绱氫俊铏熻檿鐞�銆佽闋诲湒鍍忚檿鐞嗕互鍙婃鍣ㄥ缈掓帹鐞嗙瓑銆�

鍙冩暩(sh霉)

鍨嬭櫉锛歑CVU125-2FLVA2104I
銆€銆€鍝佺墝锛歑ilinx
銆€銆€绯诲垪锛歏irtex UltraScale
銆€銆€閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃厤缃杻瀛�
銆€銆€I/O 鏁�(sh霉)閲忥細绱� 1928 鍊嬬敤鎴� I/O
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 125 钀€嬮倧杓柈鍏�
銆€銆€RAM 瀹归噺锛�6800 KB 鍒嗗竷寮� RAM 鍜屽鐙€ RAM
銆€銆€DSP 妯″鏁�(sh霉)閲忥細7800 鍊�
銆€銆€鏅傞悩绠＄悊妯″锛氶泦鎴� PLL 鍜� MMCM
銆€銆€灏佽椤炲瀷锛欶LGA (Fine Line Grid Array)
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C 鍟嗘キ(y猫)绱�

鐗规€�

XCVU125-2FLVA2104I 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鍜岄潏娲绘€�锛屾敮鎸侀珮閬� 32.75 Gbps 鐨勬敹鐧�(f膩)鍣ㄩ€熺巼锛岄仼鐢ㄤ簬鏈€鑻涘埢鐨勬暩(sh霉)鎿�(j霉)鍌宠几闇€姹傘€�
銆€銆€瀹冮倓鍏峰倷闈堟椿鐨勬灦妲�(g貌u)瑷�(sh猫)瑷�锛屽厑瑷遍枊鐧�(f膩)鑰呮牴鎿�(j霉)鍏烽珨鎳�(y墨ng)鐢ㄥ畾鍒剁‖浠跺姞閫熷櫒鍜屽崝(xi茅)铏曠悊鍣�銆�
銆€銆€瑭茶姱鐗囬泦鎴愪簡澶у閲忕殑宓屽叆寮忓瓨鍎插櫒鍜岄珮鎬ц兘 DSP 妯″锛岃兘澶犻’钁楁彁楂樻暩(sh霉)鎿�(j霉)铏曠悊鏁堢巼銆�
銆€銆€Virtex UltraScale 绯诲垪閲囩敤鍏堥€茬殑 20nm 鍒堕€犲伐钘�锛屽湪闄嶄綆鍔熻€楃殑鍚屾檪鎻愬崌浜嗘暣楂旀€ц兘銆�
銆€銆€姝ゅ锛岃┎鍣ㄤ欢鏀寔澶氱ó琛屾キ(y猫)妯欐簴鎺ュ彛鍗�(xi茅)璀�锛屽寘鎷� PCIe Gen3銆丏DR4 鍜屼互澶恫(w菐ng) MAC锛屼究浜庡揩閫熼泦鎴愬埌鐝�(xi脿n)鏈夌郴绲�(t菕ng)涓€�

鎳�(y墨ng)鐢�

XCVU125-2FLVA2104I 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂介牁(l菒ng)鍩�锛屽 4G/5G 鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙绛夎ō(sh猫)鍌欎腑銆�
銆€銆€鍚屾檪锛屽畠涔熼仼鐢ㄤ簬楂樻€ц兘瑷堢畻骞宠嚭锛屽彲鐢ㄤ簬绉戝浠跨湡銆侀噾铻嶅垎鏋愬拰鍩哄洜绲勫鐮旂┒銆�
銆€銆€鍦ㄥ伐妤�(y猫)鑷嫊鍖栨柟闈�锛岄€欐 FPGA 鍙敤浣滃鏅傛帶鍒剁郴绲�(t菕ng)鐨勬牳蹇冭檿鐞嗗櫒锛屾彁渚涚簿纰虹殑閬嬪嫊鎺у埗鍜屽京闆滅殑绠楁硶閬嬬畻鑳藉姏銆�
銆€銆€鍙﹀锛岀敱浜庡叾寮峰ぇ鐨勫苟琛岃檿鐞嗚兘鍔涘拰鍙摯灞曟€э紝XCVU125 閭勫父琚敤渚嗛枊鐧�(f膩)娣卞害瀛哥繏妯″瀷鎺ㄧ悊寮曟搸鎴栭倞绶ｆ櫤鑳界祩绔�銆�