鏅傞枔锛�2025/5/20 17:11:46
闁辫畝锛�24
XCZU19EG-1FFVB1517E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪楂樼 FPGA 鑺墖銆傝┎鍣ㄤ欢鍩轰簬 16nm FinFET 宸ヨ棟鎶�琛�(sh霉)锛屽叿鏈夐珮鎬ц兘銆侀珮闆嗘垚搴﹀拰浣庡姛鑰楃殑鐗归粸銆�
銆�銆�XCZU19EG 灞簬 Zynq UltraScale+ MPSoC 瀹舵棌锛岄泦鎴愪簡 ARM 铏曠悊鍣ㄧ郴绲�(t菕ng)鍜屽彲绶ㄧ▼閭忚集璩囨簮锛岄仼鐢ㄤ簬闇�瑕佸挤澶ц▓绠楄兘鍔涘拰闈堟椿纭欢閰嶇疆鐨勬噳鐢ㄥ牬鏅�傚叾灏佽褰㈠紡鐐� FFVB1517锛屽伐浣滈�熷害绛夌礆鐐� -1銆�
鍨嬭櫉锛歑CZU19EG-1FFVB1517E
銆�銆�宸ヨ棟绡�(ji茅)榛烇細16nm
銆�銆�鍏�(n猫i)鏍告灦妲�(g貌u)锛欰RM Cortex-A53锛�64浣嶏級鍥涙牳铏曠悊鍣� + ARM Cortex-R5 闆欐牳铏曠悊鍣�
銆�銆�FPGA 閭忚集鍠厓锛氱磩 230 钀�嬬郴绲�(t菕ng)閭忚集鍠厓
銆�銆�瀛樺劜鍣細28.8 MB 宓屽叆寮忓 RAM
銆�銆�鏁�(sh霉)瀛椾俊铏熻檿鐞嗗柈鍏冿紙DSP Slice锛夛細5,520 鍊�
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樻敮鎸� 32.75 Gbps
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 2,124 鍊嬬敤鎴� I/O
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 0.85V锛孖/O 闆诲鏍规摎(j霉)閰嶇疆鍙伕
銆�銆�灏佽锛欶FVB1517
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 85掳C锛�
XCZU19EG 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鑸囬潏娲绘��銆傚畠灏囩‖鍖栫殑 ARM 铏曠悊鍣ㄧ郴绲�(t菕ng)鑸囧彲绶ㄧ▼閭忚集鐩哥祼(ji茅)鍚堬紝浣块枊鐧�(f膩)鑰呰兘澶犲悓鏅傚埄鐢ㄨ粺浠跺拰纭欢瀵︾従(xi脿n)瑷▓鐩銆�
銆�銆�涓昏鐗规�у寘鎷細
銆�銆�1. 闆嗘垚澶氭牳 ARM Cortex-A53 鍜� Cortex-R5 铏曠悊鍣�锛岄仼鍚堥亱琛屽京闆滄搷浣滅郴绲�(t菕ng)鍜屽鏅傛帶鍒朵换鍕�銆�
銆�銆�2. 楂樺瘑搴� FPGA 鏋舵(g貌u)锛屽寘鍚ぇ閲忛倧杓柈鍏冨拰 DSP 妯″锛屾豢瓒抽珮鎬ц兘瑷堢畻闇�姹�銆�
銆�銆�3. 鏀寔澶氱ó楂橀�熸帴鍙ｆ婧�锛屽 PCIe Gen4銆丏DR4 鍏�(n猫i)瀛樻帶鍒跺櫒鍜� 100G Ethernet MAC銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄩ�熺巼鍙仈 32.75 Gbps锛岄仼閰嶆渶鏂伴�氫俊鍗�(xi茅)璀�銆�
銆�銆�5. 鍏�(n猫i)缃畨鍏ㄦ�у姛鑳�锛屼緥濡� AES 鍔犲瘑銆丼HA 鏁ｅ垪绠楁硶浠ュ強鍙俊寮曞皫姗熷埗锛岀⒑淇濇暩(sh霉)鎿�(j霉)鍌宠几鍜岃ō鍌欏暉鍕曠殑瀹夊叏鎬�銆�
銆�銆�6. 鏀寔浣庡姛鑰楁ā寮�锛岄仼鎳夊皪鑳芥晥瑕佹眰鍤存牸鐨勫祵鍏ュ紡绯荤当(t菕ng)鎳夌敤銆�
銆�銆�瑭茶姱鐗囧唬娉涙噳鐢ㄤ簬缍�(w菐ng)绲￠�氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻��銆佸伐妤�(y猫)鑷嫊鍖�銆佽埅绌鸿埅澶╁強鍦嬮槻闋樺煙銆�
XCZU19EG-1FFVB1517E 涓昏鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 缍�(w菐ng)绲￠�氫俊瑷倷锛氬璺敱鍣�銆佷氦鎻涙鍜岀劇绶氬熀绔�锛屾彁渚涢珮甯跺鍜屼綆寤堕伈鐨勬暩(sh霉)鎿�(j霉)铏曠悊鑳藉姏銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�熷崱锛氱敤浜庝汉宸ユ櫤鑳芥帹鐞�銆佽闋昏綁(zhu菐n)纰煎拰鍏朵粬楂樻�ц兘瑷堢畻浠诲嫏銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栨帶鍒讹細瀵︾従(xi脿n)瀵︽檪鐩�(ji膩n)娓�銆佹暩(sh霉)鎿�(j霉)鍒嗘瀽鍜屾帶鍒剁郴绲�(t菕ng)鍎�(y艒u)鍖�銆�
銆�銆�4. 閱�(y墨)鐧傛垚鍍忚ō鍌欙細濡傝秴鑱叉尝鍎�鍣ㄥ拰 CT 鎺冩弿鍎�锛岃檿鐞嗗京闆滅殑鍦栧儚閲嶅缓绠楁硶銆�
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃诧細闁嬬櫦(f膩)闆烽仈绯荤当(t菕ng)銆佽(w猫i)鏄熼�氫俊绲傜鍜屽畨鍏ㄥ姞瀵嗚缃�銆�
銆�銆�6. 鑷嫊椐曢姹借粖锛氳矤璨挵(hu谩n)澧冩劅鐭�銆佽矾寰戣(gu墨)鍔冨拰姹虹瓥鍒跺畾绛夐棞閸典换鍕欍��
XCZU17EG-1FFVB1517E
銆�銆�XCZU23EG-1FFVB1517E
銆�銆�XCZU28EV-1FFVC1760E
