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鎮ㄥソ锛屾杩庝締(l谩i)鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > XCZU4EV-2FBVB900E

XCZU4EV-2FBVB900E 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/4/25 15:41:54 鏌ョ湅 闁辫畝锛�41

XCZU4EV-2FBVB900E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq UltraScale+ MPSoC 绯诲垪涓殑涓�鍊�(g猫)楂樼鍨嬭櫉(h脿o)銆傝┎鑺墖鍩轰簬 16nm FinFET 宸ヨ棟鎶�琛�(sh霉)锛岄泦鎴愪簡 ARM Cortex-A53 鍜� Cortex-R5 铏曠悊鍣ㄥ収(n猫i)鏍革紝鍚屾檪(sh铆)閭勫寘鍚挤(qi谩ng)澶х殑 FPGA 鍙法绋嬮倧杓硣婧�銆佸湒褰㈣檿鐞嗗柈鍏冿紙GPU锛変互鍙婅睈瀵岀殑澶栬ō(sh猫)鎺ュ彛銆�
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鍙冩暩(sh霉)

宸ヨ棟锛�16nm
銆�銆�灏佽椤炲瀷锛欶BGA
銆�銆�寮曡叧鏁�(sh霉)锛�900
銆�銆�铏曠悊鍣ㄦ灦妲�(g貌u)锛欰RM Cortex-A53 (64-bit) + ARM Cortex-R5
銆�銆�瀛樺劜(ch菙)鍣細楂橀仈(d谩) 6.8 Mb 宓屽叆寮忓 RAM
銆�銆�鍙法绋嬮倧杓細绱� 43K 閭忚集鍠厓
銆�銆�DSP 鐗囨暩(sh霉)閲忥細绱� 2200 DSP slices
銆�銆�I/O 鏁�(sh霉)閲忥細绱� 375 I/Os
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�渚涢浕闆诲锛氬闆诲鍩熻ō(sh猫)瑷�(j矛)锛屾牳蹇冮浕澹撶磩鐐� 0.85V

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XCZU4EV-2FBVB900E 鎻愪緵浜嗛珮搴﹂泦鎴愮殑绯荤当(t菕ng)绱�(j铆)瑙ｆ焙鏂规锛屽叿鏈変互涓嬮’钁楃壒榛�(di菐n)锛�
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銆�銆�1. 宸ユキ(y猫)鑷嫊(d貌ng)鍖栵細鐢ㄤ簬閬�(y霉n)鍕�(d貌ng)鎺у埗銆佹(j墨)鍣ㄤ汉瑕栬(ju茅)鍜屽伐寤犵洠(ji膩n)鎺х瓑闋�(l菒ng)鍩�銆�
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鏇夸唬鍨嬭櫉(h脿o)

XCZU5EV-2FFVG1156E
銆�銆�XCZU3EG-2FFVC1156E
銆�銆�XCZU4CG-2FFVC900E

xczu4ev-2fbvb900e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

xczu4ev-2fbvb900e鍙冩暩(sh霉)

  • 鐝�(xi脿n)鏈夋暩(sh霉)閲�0鐝�(xi脿n)璨ㄦ煡鐪嬩氦鏈�
  • 鍍�(ji脿)鏍�1 : 锟�18,334.46000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EV
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  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
  • 鏋舵(g貌u)MCU锛孎(xi脿n)PGA
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  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
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  • 灏佽/澶栨900-BBGA锛孎(xi脿n)CBGA
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