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闁辫畝锛�27
XCZU6CG-1FFVB1156E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq UltraScale+ MPSoC 绯诲垪涓殑涓�鍊嬮珮绔瀷铏熴�傝┎绯诲垪闆嗘垚浜� ARM 铏曠悊鍣ㄥ拰 FPGA 鏋舵锛屾彁渚涢珮鎬ц兘瑷堢畻鑳藉姏銆侀潏娲荤殑鍙法绋嬮倧杓互鍙婁綆鍔熻�楃壒鎬�銆�
銆�銆�XCZU6CG 鍖呭惈闆欐牳 ARM Cortex-A53 鍜岄洐鏍� ARM Cortex-R5 铏曠悊鍣紝閬╁悎闇�瑕佸鏅傝檿鐞嗗拰楂樺付瀵殑鎳夌敤鍫存櫙銆傛澶栵紝瀹冮倓鍏峰倷寮峰ぇ鐨� DSP 寮曟搸銆侀珮閫熸敹鐧�(f膩)鍣紙鏈�楂� 32.75Gbps锛夊拰璞愬瘜鐨勫瑷帴鍙�銆�
灏佽锛欶FVB1156
銆�銆�鍏ф牳鏁�(sh霉)閲忥細2鍊� ARM Cortex-A53 + 2鍊� ARM Cortex-R5
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�FPGA 閭忚集鍠厓锛氱磩 429K
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銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 0.85V锛孖/O 闆诲 1.8V/2.5V/3.3V
XCZU6CG 鎻愪緵浜嗛珮搴﹂泦鎴愮殑瑷▓鏂规锛岀祼鍚堜簡铏曠悊鍣ㄥ瓙绯荤当(t菕ng)锛圥S锛夊拰鍙法绋嬮倧杓瓙绯荤当(t菕ng)锛圥L锛�銆�
銆�銆�1. PS 閮ㄥ垎鍖呮嫭闆欐牳 ARM Cortex-A53 鍜岄洐鏍� ARM Cortex-R5锛屾敮鎸� Linux 鎿嶄綔绯荤当(t菕ng)鍜屽鏅備换鍕欑鐞�銆�
銆�銆�2. PL 閮ㄥ垎鎻愪緵 FPGA 鐨勯潏娲绘�э紝鍏佽ū鐢ㄦ埗鑷畾缇╃‖浠跺姞閫熸ā濉�銆�
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XCZU6CG 寤ｆ硾鎳夌敤浜庡皪鎬ц兘鍜岄潏娲绘�ц姹傝純楂樼殑闋樺煙锛�
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銆�銆�5. 閭婄罚瑷堢畻骞宠嚭锛岀偤鏅鸿兘鍩庡競鍜屾櫤鑳藉灞呮彁渚涙湰鍦板寲绠楀姏鏀寔銆�
XCZU7EV-1FFVC1156E
銆�銆�XCZU5EV-1FFVG900E
銆�銆�XCZU4CG-1FFVB1156E
