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EP4CE22F17I8LN 鏄� Altera锛堢従(xi脿n)鐐� Intel FPGA 閮ㄩ杸锛夋帹鍑虹殑 Cyclone IV 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏熴�傝┎绯诲垪 FPGA 浠ュ叾楂樻�ц兘銆佷綆鍔熻�楀拰楂樻�у児姣旇憲绋憋紝閬╃敤浜庡绋祵鍏ュ紡绯荤当(t菕ng)瑷▓鍫存櫙銆�
銆�銆�閫欐鑺墖鍏ч儴闆嗘垚浜嗚睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏熻檿鐞嗭紙DSP锛夋ā濉婁互鍙婂祵鍏ュ紡瀛樺劜鍣ㄥ锛屽悓鏅傛敮鎸佸绋珮閫熸帴鍙ｆ婧栵紝閬╁悎鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆佹秷璨婚浕瀛愪互鍙婃苯杌婇浕瀛愮瓑闋樺煙銆�
鍨嬭櫉锛欵P4CE22F17I8LN
銆�銆�绯诲垪锛欳yclone IV
銆�銆�鍝佺墝锛欰ltera (Intel FPGA)
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細21,760
銆�銆�DSP 妯″鏁�(sh霉)閲忥細96
銆�銆�RAM 浣嶅锛�310.5Kb
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細172
銆�銆�閰嶇疆妯″紡锛氫富鍕曚覆琛� (AS), 琚嫊涓茶 (PS), JTAG
銆�銆�灏佽椤炲瀷锛欶BGA
銆�銆�鏍稿績闆诲锛�1.2V
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
EP4CE22F17I8LN 鎻愪緵浜嗛潏娲荤殑鍙法绋嬮倧杓硣婧�锛岃兘澶犳豢瓒冲绋京闆滃姛鑳界殑闇�姹傘��
銆�銆�瀹冨収缃簡 96 鍊� DSP 妯″锛屽彲浠ラ珮鏁堝鐝�(xi脿n)鍚勭ó鏁�(sh霉)瀛椾俊铏熻檿鐞嗙畻娉�锛屼緥濡傛烤娉�銆丗FT 鍜岀煩闄ｉ亱绠楃瓑銆�
銆�銆�鑺墖鍏у祵鐨勫ぇ瀹归噺 RAM 璩囨簮鍏佽ū鐢ㄦ埗妲嬪缓寰╅洔鐨勫瓨鍎茬祼妲嬫垨鏁�(sh霉)鎿�(j霉)绶╂矕鍗�(q奴)锛屽緸鑰屾笡灏戝皪澶栭儴瀛樺劜鍣ㄧ殑渚濊炒銆�
銆�銆�鍏� I/O 寮曡叧鏀寔澶氱ó妯欐簴锛屽寘鎷� LVCMOS銆丩VDS 鍜屽樊鍒嗚几鍏ヨ几鍑�锛屾柟渚胯垏澶栭儴瑷倷閫茶閫氫俊銆�
銆�銆�姝ゅ锛岃┎鑺墖閭勫叿鏈変綆鍔熻�楃殑鐗归粸锛岄潪甯搁仼鍚堜究鏀滃紡瑷倷鎴栧皪鑳芥晥鏈夎純楂樿姹傜殑鎳夌敤鐠�(hu谩n)澧�銆�
EP4CE22F17I8LN 寤ｆ硾鎳夌敤浜庡鍊嬮牁鍩燂細
銆�銆�1. 宓屽叆寮忕郴绲�(t菕ng)闁嬬櫦(f膩)锛屽瑕栭牷铏曠悊銆佸湒鍍忚瓨鍒ュ拰閬嬪嫊鎺у埗銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栦腑锛屽彲鐢ㄤ簬瀵︽檪鏁�(sh霉)鎿�(j霉)閲囬泦鑸囩洠(ji膩n)鎺х郴绲�(t菕ng)銆�
銆�銆�3. 閫氫俊闋樺煙锛屼緥濡傚熀绔欐帶鍒跺櫒銆佸崝(xi茅)璀拌綁鎻涘櫒鍜岀恫绲′氦鎻涙銆�
銆�銆�4. 姹借粖闆诲瓙涓殑椐曢杓斿姪绯荤当(t菕ng)鍜屼俊鎭妯傜郴绲�(t菕ng)銆�
銆�銆�5. 閱�(y墨)鐧傝ō鍌欎腑鐨勪俊铏熻檿鐞嗗柈鍏冨拰瑷烘柗鍎�鍣�銆�
銆�銆�鐢变簬鍏跺挤澶х殑閭忚集璩囨簮鍜� DSP 鍔熻兘锛岄�欐 FPGA 鍦ㄩ渶瑕佸鏅傝▓绠楀拰鏁�(sh霉)鎿�(j霉)铏曠悊鐨勫湴鏂硅〃鐝�(xi脿n)灏ょ偤绐佸嚭銆�
EP4CE15F17C8, EP4CE30F17C8N
