K4B2G1646C-HCK0 鏅傞枔锛�2025/4/30 11:13:11 闁辫畝锛�32

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椤炲瀷锛欴DR3 SDRAM
銆€銆€瀹归噺锛�2Gb (256Mb x 8)
銆€銆€绲勭箶鏂瑰紡锛�8-bank architecture
銆€銆€鏁�(sh霉)鎿�(j霉)瀵害锛歺8
銆€銆€宸ヤ綔闆诲锛�1.35V 鎴� 1.5V
銆€銆€I/O 闆诲锛�1.5V
銆€銆€灏佽褰㈠紡锛欶BGA (Fine Pitch Ball Grid Array)
銆€銆€寮曡叧鏁�(sh霉)锛�78鐞�
銆€銆€鏁�(sh霉)鎿�(j霉)鍌宠几閫熺巼锛�1600Mbps
銆€銆€CAS寤堕伈锛欳L=11
銆€銆€婧害鑼冨湇锛�0掳C 鑷� 85掳C

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