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鍙冩暩(sh霉)

渚涢浕闆诲锛�1.8V~3.3V
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40鈩冭嚦+85鈩�
銆€銆€灏佽褰㈠紡锛歍SSOP
銆€銆€閫氶亾鏁�(sh霉)锛�
銆€銆€杓稿嚭椤炲瀷锛歀VPECL/LVDS/HCSL/CML/TTL/CMOS
銆€銆€鎶栧嫊(d貌ng)锛氬吀鍨嬪€肩偤25fs RMS
銆€銆€闋荤巼鑼冨湇锛氭渶楂樻敮鎸佽嚦1.6GHz

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LMK107B7474MA-T 鎻愪緵浜嗗绋棞(gu膩n)閸电壒鎬у拰鍎�(y艒u)鍕�(sh矛)锛�
銆€銆€1. 妤典綆鐨勭浉浣嶆姈鍕�(d貌ng)锛屼娇鍏堕潪甯搁仼鍚堥珮鎬ц兘鏅�(sh铆)閻樺垎閰嶆噳(y墨ng)鐢ㄣ€�
銆€銆€2. 鏀寔澶氶仈(d谩)7鍊�(g猫)杓稿嚭閫氶亾锛屽厑瑷遍潏娲婚厤缃笉鍚岄鍨嬬殑鏅�(sh铆)閻樹俊铏�(h脿o)銆�
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LMK107B7474MA-T 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂借ō(sh猫)鍌欙紝渚嬪鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙(j墨)涓殑鏅�(sh铆)閻樺垎閰嶃€�
銆€銆€2. 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涚郴绲�(t菕ng)锛屽寘鎷珮閫熸ā鏁�(sh霉)杞�(zhu菐n)鎻涘櫒 (ADC) 鍜屾暩(sh霉)妯¤綁(zhu菐n)鎻涘櫒 (DAC) 鐨勬檪(sh铆)閻樼敓鎴愩€�
銆€銆€3. FPGA 鍜� ASIC 瑷�(sh猫)瑷�(j矛)涓殑鍙冭€冩檪(sh铆)閻樻ā濉�銆�
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