鏅傞枔锛�2025/4/29 14:02:47
闁辫畝锛�38
XCKU115-3FLVD1517E 鏄竴娆剧敱 Xilinx 鍏徃鐢熺敘鐨� Kintex UltraScale 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪鑺墖鍩轰簬 20nm 宸ヨ棟鍒剁▼锛屽叿鏈夐珮甯跺銆佷綆寤堕伈鍜屽彲鎿村睍鎬у挤鐨勭壒榛�锛岄仼鐢ㄤ簬楂樻�ц兘瑷堢畻銆侀�氫俊鍩虹瑷柦銆佽埅绌鸿埅澶╄垏鍦嬮槻绛夐牁鍩熺殑寰╅洔瑷▓闇�姹�銆�
銆�銆�瑭插瀷铏熺殑 FPGA 鎻愪緵浜嗚睈瀵岀殑閭忚集璩囨簮銆丏SP 妯″浠ュ強楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛屾敮鎸佸绋帴鍙ｅ崝(xi茅)璀�锛屼緥濡� PCIe銆丏DR4 鍜� CPRI 绛�锛岃兘澶犳豢瓒冲妯ｅ寲鐨勮ō瑷堣姹傘��
閭忚集鍠厓锛�115K
銆�銆�閰嶇疆妯″紡锛氬柈 boot SPI Flash
銆�銆�I/O 鏁搁噺锛�844
銆�銆�DSP Slice锛�2880
銆�銆�鍏ч儴瀛樺劜鍣細6800 KB
銆�銆�鏈�澶у伐浣滈牷鐜囷細1000 MHz
銆�銆�宸ヨ棟鍒剁▼锛�20 nm
銆�銆�渚涢浕闆诲锛�1.0V 鏍稿績闆诲, 1.8V I/O 闆诲
銆�銆�灏佽椤炲瀷锛欶FG1517
XCKU115-3FLVD1517E 鎻愪緵寮峰ぇ鐨勫苟琛岃檿鐞嗚兘鍔�锛岄仼鍚堥渶瑕佸鏅傛暩鎿氳檿鐞嗙殑鎳夌敤鍫存櫙銆傚畠闆嗘垚浜嗗ぇ閲� DSP 妯″锛屽彲浠ュ姞閫熸暩瀛搁亱绠楀拰淇¤櫉铏曠悊浠诲嫏銆傛澶�锛岄�欐 FPGA 鏀寔楂橀仈 32.75 Gbps 鐨勯珮閫熸敹鐧�(f膩)鍣ㄩ�熺巼锛屽苟涓斿吋瀹硅姱鐗囬倓鍏峰倷闈堟椿鐨勬檪閻樼鐞嗗姛鑳藉拰璞愬瘜鐨勮瑭﹀伐鍏�锛屼究浜庨枊鐧�(f膩)浜哄摗鍎�(y艒u)鍖栬ō瑷堟�ц兘銆傞�氶亷浣跨敤 Vivado 瑷▓濂椾欢锛屽伐绋嬪斧鍙互杓曟澗瀵︾従(xi脿n)楂樺堡娆＄稖鍚堝拰 IP 闆嗘垚锛屽緸鑰屽姞蹇敘鍝佷笂甯傛檪闁�銆�
銆�銆�鍚屾檪锛孠intex UltraScale 绯诲垪鍦ㄥ姛鑰楁帶鍒舵柟闈㈣〃鐝�(xi脿n)鍑鸿壊锛岃兘澶犲湪淇濊瓑鎬ц兘鐨勫悓鏅傞檷浣庤兘婧愭秷鑰�銆�
瑭� FPGA 寤ｆ硾鎳夌敤浜庣劇绶氬熀绔欍�佹湁绶氱恫绲¤ō鍌�銆佽闋诲唬鎾郴绲�(t菕ng)銆佸湒鍍忚檿鐞嗗钩鑷轰互鍙婇浄閬旂郴绲�(t菕ng)绛夐牁鍩�銆傚叿楂斿寘鎷細
銆�銆�1. 閫氫俊闋樺煙 - 瀵︾従(xi脿n) MAC/PHY 灞ゅ姛鑳�銆佸墠鍌�/鍥炲偝閺堣矾铏曠悊銆�
銆�銆�2. 鏁告摎涓績 - 鍩�(zh铆)琛屽寘鍒嗛銆佸姞瀵嗚В瀵嗘搷浣�銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖� - 鎺у埗姗熷櫒浜洪亱鍕曘�佺洠(ji膩n)娓伐妤�(y猫)鍌虫劅鍣ㄦ暩鎿�銆�
銆�銆�4. 閱�(y墨)鐧傛垚鍍� - 铏曠悊 CT銆丮RI 鍦栧儚閲嶅缓绠楁硶銆�
銆�銆�5. 杌嶄簨鍦嬮槻 - 闁嬬櫦(f膩)闆诲瓙灏嶆姉瑷倷鍙婂皫鑸郴绲�(t菕ng)銆�
XCKU060-1FFVB1156E, XCKU040-2FFVA1156E
