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銆�銆�XCVU095 琛ㄧず瑭� FPGA 灞簬 Virtex UltraScale+ 绯诲垪锛屾搧鏈� 95K 鐨勯倧杓柈鍏冩暩閲忥紙绱勭瓑浜� 95000 鍊嬪彲绶ㄧ▼閭忚集鍠厓锛�銆傚叾灏佽褰㈠紡鐐� FFVC1517锛屾槸涓�绋� BGA 灏佽椤炲瀷锛屽叿鍌欏劒(y艒u)绉�鐨勬暎鐔辨�ц兘鍜岄浕姘ｇ壒鎬с��
鍨嬭櫉锛歑CVU095-2FFVC1517E
銆�銆�宸ヨ棟锛�16nm
銆�銆�閭忚集鍠厓锛�95K
銆�銆�閰嶇疆闁冨瓨锛氬缃�
銆�銆�瀛樺劜濉婏細28.8MB
銆�銆�DSP Slice 鏁搁噺锛�5880
銆�銆�I/O 鏁搁噺锛�1232
銆�銆�鏈�澶у伐浣滈牷鐜囷細~1GHz
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75Gbps
銆�銆�渚涢浕闆诲锛�0.8V 鏍稿績锛�1.0V 杓斿姪闆昏矾
銆�銆�灏佽锛欶FVC1517
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銆�銆�鍚屾檪锛岄�欐 FPGA 鏀寔纭牳铏曠悊鍣ㄧ郴绲�(t菕ng)锛圚PS锛�锛屽厑瑷辩敤鎴堕泦鎴� ARM Cortex-A53 澶氭牳铏曠悊鍣ㄧ敤浜庡祵鍏ュ紡鎳夌敤闁嬬櫦(f膩)銆傞�氶亷 PCIe Gen4 鍜� CCIX 绛夊厛閫插崝(xi茅)璀扮殑鏀寔锛岃┎鑺墖鍦ㄦ暩鎿氬悶鍚愰噺鍜屽欢閬叉柟闈㈣〃鐝惧嚭鑹�銆�
銆�銆�鍙﹀锛孹CVU095 鎻愪緵浜嗛潏娲荤殑鏅傞悩绠＄悊宸ュ叿锛圕lock Management Tile锛�锛屽寘鎷� PLL 鍜� MMCM 妯″锛屾湁鍔╀簬鐢熸垚绮剧⒑涓斾綆鎶栧嫊鐨勬檪閻樹俊铏�銆傛渶鍚�锛孹ilinx 鎻愪緵浜嗗畬鏁寸殑闁嬬櫦(f膩)鐠�(hu谩n)澧� Vivado锛屽公鍔╁伐绋嬪斧蹇�熶笂鎵嬪苟鍎�(y艒u)鍖栬ō瑷堟祦绋�銆�
瑭插瀷铏� FPGA 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 楂橀�熺恫绲′氦鎻涙鑸囪矾鐢卞櫒
銆�銆�2. 鏁告摎涓績鏈嶅嫏鍣ㄥ姞閫熷崱
銆�銆�3. 瑕栭牷寤ｆ挱瑷倷鍙婂湒鍍忚檿鐞嗙郴绲�(t菕ng)
銆�銆�4. 閱�(y墨)鐧傛垚鍍忓剙鍣�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栨帶鍒�
銆�銆�6. ADAS锛堥珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛夊拰鑷嫊椐曢鐩搁棞纭欢
銆�銆�7. 鐒＄窔閫氫俊鍩虹瑷柦锛屼緥濡� 5G 鍩虹珯
銆�銆�8. 鍔犲瘑璨ㄥ梗鎸栫う ASIC 鍘熷瀷椹楄瓑骞宠嚭
銆�銆�鐢变簬鍏跺挤澶х殑鍔熻兘闆嗗悎鍜屾摯灞曡兘鍔�锛孹CVU095-2FFVC1517E 鎴愮偤鐪惧寰╅洔闆诲瓙绯荤当(t菕ng)鐨勭悊鎯抽伕鎿�銆�
XCVU095-1FFVC1517E
銆�銆�XCVU095-3FFVC1517E
