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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU19EG-2FFVE1924I

XCZU19EG-2FFVE1924I 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/4/28 16:35:16 鏌ョ湅 闁辫畝锛�42

XCZU19EG-2FFVE1924I 鏄竴娆剧敱 Xilinx锛堢従(xi脿n)鐐� AMD 鑷仼鎳�(y墨ng)瑷堢畻閮ㄩ杸锛夌敓鐢�(ch菐n)鐨勯珮鎬ц兘 Zynq UltraScale+ MPSoC 绯诲垪鑺墖銆傝┎鍣ㄤ欢闆嗘垚浜嗗彲绶ㄧ▼閭忚集銆佽檿鐞嗗櫒绯荤当(t菕ng)鍜屽皥鐢ㄧ‖浠跺姞閫熸ā濉�锛岄仼鍚堢敤浜庨�氫俊銆佹暩(sh霉)鎿�(j霉)涓績銆佽埅绌鸿埅澶┿�佸伐妤�(y猫)鑷嫊鍖栫瓑闋�(l菒ng)鍩熺殑寰�(f霉)闆滄噳(y墨ng)鐢�銆�
銆�銆�XCZU19EG 鏄暣鍊嬬郴鍒椾腑鍔熻兘鏈�寮�(qi谩ng)澶х殑鍨嬭櫉涔嬩竴锛岄噰鐢� 16nm FinFET 宸ヨ棟鍒堕��锛屾彁渚涙サ楂樼殑闆嗘垚搴﹁垏鎬ц兘锛屾敮鎸佸(sh铆)鏅傝檿鐞嗗拰闈堟椿鐨勭‖浠跺畾鍒惰兘鍔�銆�

鍙冩暩(sh霉)

椤炲瀷锛歁PSoC
銆�銆�宸ヨ棟锛�16nm
銆�銆�TDP锛�10-30W锛堟牴鎿�(j霉)閰嶇疆涓嶅悓鑰岃畩鍖栵級
銆�銆�鍏�(n猫i)鏍革細鍥涙牳 ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�鍙法绋嬮倧杓柈鍏冿細绱� 247K 閭忚集鍠厓
銆�銆�DSP 鐗囨暩(sh霉)锛�5,840 DSP Slices
銆�銆�濉婂瓨鍎插櫒锛氱磩 28.4MB BRAM
銆�銆�楂橀�熸帴鍙ｏ細PCIe Gen3 x8銆�100G Ethernet銆丆CIX
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 3,464 鍊嬬敤鎴� I/O
銆�銆�灏佽锛欶FVE1924

鐗规��

XCZU19EG 鎻愪緵浜嗛潪甯搁珮鐨勬�ц兘鍜岄潏娲绘�э紝鍏朵富瑕佺壒鎬у寘鎷細
銆�銆�1. 闆嗘垚鐨勫鏍歌檿鐞嗗櫒绯荤当(t菕ng)锛屽寘鎷珮鏁堣兘鐨� ARM Cortex-A53 鍜屽(sh铆)鏅傛帶鍒剁敤鐨� ARM Cortex-R5 鏍稿績锛屾敮鎸佺暟妲�(g貌u)澶氫换鍕�(w霉)閬�(y霉n)琛�銆�
銆�銆�2. 瓒呭ぇ瑕�(gu墨)妯＄殑 FPGA 鏋舵(g貌u)锛屽叿鏈夊閬�(d谩) 247K 閭忚集鍠厓鍜� 5,840 鍊� DSP Slice锛屾豢瓒冲京(f霉)闆滅畻娉曞(sh铆)鐝�(xi脿n)鐨勯渶姹�銆�
銆�銆�3. 鏀寔澶氱ó楂橀�熸帴鍙ｆ(bi膩o)婧�(zh菙n)锛屽 PCIe Gen3銆�100G Ethernet 鍜� CCIX锛岄仼鐢ㄤ簬楂樺付瀵暩(sh霉)鎿�(j霉)鍌宠几鍫存櫙銆�
銆�銆�4. 鍏�(n猫i)缃畨鍏ㄥ暉鍕曞姛鑳藉拰鍔犲瘑寮曟搸锛岀⒑淇濊ō(sh猫)鍌欑殑瀹夊叏鎬�銆�
銆�銆�5. 鏀寔鍕曟厠(t脿i)鍔熻兘浜ゆ彌锛圖FX锛�锛屽厑瑷遍儴鍒嗛噸鏂伴厤缃互鍎�(y艒u)鍖栬硣婧愬埄鐢ㄣ��
銆�銆�6. 鎻愪緵瀹屾暣鐨勯枊鐧�(f膩)宸ュ叿閺�锛屽寘鎷� Vivado Design Suite 鍜� Vitis 杌熶欢骞宠嚭锛岀啊鍖栧緸纭欢瑷�(sh猫)瑷堝埌杌熶欢闁嬬櫦(f膩)鐨勬祦绋�銆�

鎳�(y墨ng)鐢�

閫欐鑺墖寤ｆ硾鎳�(y墨ng)鐢ㄤ簬闇�瑕侀珮鎬ц兘瑷堢畻鍜屽(sh铆)鏅傝檿鐞嗚兘鍔涚殑闋�(l菒ng)鍩燂紝渚嬪锛�
銆�銆�1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細5G 鍩虹珯銆佺恫(w菐ng)绲�(lu貌)璺敱鍣ㄥ拰浜ゆ彌姗�(j墨)銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細AI 鎺ㄧ悊銆佽闋昏綁(zhu菐n)纰�銆佹暩(sh霉)鎿�(j霉)澹撶府绛変换鍕�(w霉)銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細姗�(j墨)鍣ㄤ汉鎺у埗銆佸伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)缍�(w菐ng)闂�(gu膩n)銆�
銆�銆�4. 姹借粖闆诲瓙锛氶珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛�銆佽嚜鍕曢椐�銆�
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃诧細闆烽仈(d谩)淇¤櫉铏曠悊銆佽(w猫i)鏄熼�氫俊銆�

鏇夸唬鍨嬭櫉

XCZU19EG-2FFVG1960E, XCZU19EG-2FFVC1760E

xczu19eg-2ffve1924i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xczu19eg-2ffve1924i鍙冩暩(sh霉)

  • 鐝�(xi脿n)鏈夋暩(sh霉)閲�0鐝�(xi脿n)璨ㄦ煡鐪嬩氦鏈�
  • 鍍规牸1 : 锟�80,652.08000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
  • 鍖呰鎵樼洡
  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
  • 鏋舵(g貌u)MCU锛孎(xi脿n)PGA
  • 鏍稿績铏曠悊鍣�甯� CoreSight? 鐨勫洓鏍� ARM? Cortex?-A53 MPCore?锛屽付 CoreSight? 鐨勯洐鏍� ARM?Cortex?-R5锛孉RM Mali?-400 MP2
  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
  • 閫熷害533MHz锛�600MHz锛�1.3GHz
  • 涓昏灞��Zynq?UltraScale+? FPGA锛�1143K+ 閭忚集鍠厓
  • 宸ヤ綔婧害-40掳C ~ 100掳C锛圱J锛�
  • 灏佽/澶栨1924-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�1924-FCBGA锛�45x45锛�